{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T14:12:56Z","timestamp":1774966376013,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"National Sustainability Program","award":["LO1401"],"award-info":[{"award-number":["LO1401"]}]},{"DOI":"10.13039\/501100001824","name":"Czech Science Foundation","doi-asserted-by":"crossref","award":["P102-15-21942S"],"award-info":[{"award-number":["P102-15-21942S"]}],"id":[{"id":"10.13039\/501100001824","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/tvlsi.2018.2878625","type":"journal-article","created":{"date-parts":[[2018,11,15]],"date-time":"2018-11-15T21:19:56Z","timestamp":1542316796000},"page":"316-325","source":"Crossref","is-referenced-by-count":23,"title":["A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta\u2013Sigma Modulator in 0.18-<inline-formula> \n                     <tex-math notation=\"LaTeX\">$\\mu$ <\/tex-math>\n                  <\/inline-formula>m CMOS"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6315-9292","authenticated-orcid":false,"given":"Tomasz","family":"Kulej","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9864-9830","authenticated-orcid":false,"given":"Fabian","family":"Khateb","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0189-036X","authenticated-orcid":false,"given":"Luis H. C.","family":"Ferreira","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2043169"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2198981"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-014-9906-2"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2012.0372"},{"key":"ref14","author":"allen","year":"2012","journal-title":"CMOS Analog Circuit Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848021"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2468857"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2753841"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.4437"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-014-0385-y"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2330698"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2179732"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/82.644044"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2741343"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2465"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2289413"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864147"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8628286\/08536916.pdf?arnumber=8536916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:10:24Z","timestamp":1657746624000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8536916\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":18,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2878625","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,2]]}}}