{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T21:22:58Z","timestamp":1775683378105,"version":"3.50.1"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61674002"],"award-info":[{"award-number":["61674002"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61474001"],"award-info":[{"award-number":["61474001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"National Science and Technology Major Project","award":["2017ZX01028-101-003"],"award-info":[{"award-number":["2017ZX01028-101-003"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/tvlsi.2018.2879341","type":"journal-article","created":{"date-parts":[[2018,11,20]],"date-time":"2018-11-20T20:02:12Z","timestamp":1542744132000},"page":"407-415","source":"Crossref","is-referenced-by-count":164,"title":["Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2408-5048","authenticated-orcid":false,"given":"Chunyu","family":"Peng","sequence":"first","affiliation":[]},{"given":"Jiati","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Changyong","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Qiang","family":"Zhao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3249-2401","authenticated-orcid":false,"given":"Songsong","family":"Xiao","sequence":"additional","affiliation":[]},{"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3314-1606","authenticated-orcid":false,"given":"Zhiting","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8097-4053","authenticated-orcid":false,"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2304658"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2014.2361514"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2016.2593590"},{"key":"ref13","first-page":"203","article-title":"LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design","author":"kelin","year":"2010","journal-title":"Proc IEEE Int Rel Phys Symp"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2010.2073486"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2627003"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2449073"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2011.12.002"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2191971"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1587\/elex.14.20170784"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2011.2167233"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763020"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/7298.946456"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2047907"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/23.556880"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2009.2032090"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2013.2260357"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2003.813129"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2015.2456832"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2659382"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2677904"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2637322"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2011.2157506"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8628286\/08540875.pdf?arnumber=8540875","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:08:29Z","timestamp":1657746509000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8540875\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":23,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2879341","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,2]]}}}