{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:50:23Z","timestamp":1771703423279,"version":"3.50.1"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"DOI":"10.13039\/501100001711","name":"Schweizerischer Nationalfonds zur F\u00f6rderung der Wissenschaftlichen Forschung","doi-asserted-by":"publisher","award":["200021-146600"],"award-info":[{"award-number":["200021-146600"]}],"id":[{"id":"10.13039\/501100001711","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001742","name":"United States-Israel Binational Science Foundation","doi-asserted-by":"publisher","award":["2016016"],"award-info":[{"award-number":["2016016"]}],"id":[{"id":"10.13039\/501100001742","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["FA8650-18-2-7855"],"award-info":[{"award-number":["FA8650-18-2-7855"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tvlsi.2018.2883923","type":"journal-article","created":{"date-parts":[[2018,12,14]],"date-time":"2018-12-14T22:25:05Z","timestamp":1544826305000},"page":"637-650","source":"Crossref","is-referenced-by-count":17,"title":["FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2203-3981","authenticated-orcid":false,"given":"Xifan","family":"Tang","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5415-1870","authenticated-orcid":false,"given":"Edouard","family":"Giacomin","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7827-3215","authenticated-orcid":false,"given":"Giovanni De","family":"Micheli","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3634-3999","authenticated-orcid":false,"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","author":"albrecht","year":"2005","journal-title":"IWLS 2005 Benchmarks"},{"key":"ref38","author":"yang","year":"1991","journal-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3 0"},{"key":"ref33","year":"2011","journal-title":"Interconnect chapter"},{"key":"ref32","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2006.270299"},{"key":"ref30","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2004.1393249"},{"key":"ref36","year":"2017","journal-title":"ModelSim ASIC and FPGA Design"},{"key":"ref35","year":"2017","journal-title":"HSPICE The Gold Standard for Accurate Circuit Simulation"},{"key":"ref34","year":"2016","journal-title":"Innovus Implementation System"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/360276.360299"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"155","DOI":"10.1145\/329166.329199","article-title":"Generating highly-routable sparse crossbars for PLDs","author":"lemieuxm","year":"2000","journal-title":"Proc ACM Int Symp Field-Program Gate Arrays (FPGA)"},{"key":"ref29","first-page":"87","article-title":"A 65 nm flash-based FPGA fabric optimized for low cost and power","author":"greene","year":"2001","journal-title":"Proc ACM Int Symp Field-Program Gate Arrays (FPGA)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311199"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"key":"ref22","year":"2008","journal-title":"Virtex-5 User Guide uG190 (v4 0)"},{"key":"ref21","year":"2008","journal-title":"Stratix IV Device Handbook Version SIV5V1-1 1"},{"key":"ref24","year":"2015","journal-title":"Virtex-7 User Guide DS180 (V1 17)"},{"key":"ref23","year":"2015","journal-title":"Stratix 10 Advance Information Brief"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.25"},{"key":"ref25","first-page":"135","article-title":"Improving FPGA performance and area using an adaptive logic module","author":"hutton","year":"2004","journal-title":"Proc Int Conf Field Program Logic Appl (FPL)"},{"key":"ref50","first-page":"452","article-title":"A 460 MHz at 397mV, 2.6 GHz at 1.3 V, 32b VLIW DSP, embedding $\\text{F}_{\\mathrm{ MAX}}$ tracking","author":"wilson","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1145\/1463768.1463784"},{"key":"ref54","first-page":"1","article-title":"TinySPICE Plus: Scaling up statistical SPICE simulations on GPU leveraging shared-memory based sparse matrix solution techniques","author":"han","year":"2016","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2173199"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796514"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645511"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577325"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357183"},{"key":"ref13","year":"2018","journal-title":"Open Project"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046220"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3024063"},{"key":"ref16","article-title":"Thermal management techniques for field programmable gate arrays","author":"deshpande","year":"2017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950437"},{"key":"ref18","first-page":"1","article-title":"Accurate power analysis for near-Vt RRAM-based FPGA","author":"tang","year":"2015","journal-title":"Proc Int Conf Field Program Logic Appl (FPL)"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2847600"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508150"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950457"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852293"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412139"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MCSoC.2015.44"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234250"},{"key":"ref9","author":"betz","year":"1998","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996675"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/92.784093"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/4.535416"},{"key":"ref47","first-page":"657","article-title":"Methodology for high level estimation of FPGA power consumption","author":"degalahal","year":"2005","journal-title":"Proc Asia South Pacific Des Autom Conf (ASP-DAC)"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/92.335013"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887920"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISIEA.2010.5679428"},{"key":"ref43","author":"vladimirescu","year":"2012","journal-title":"The SPICE Book"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8649697\/08576622.pdf?arnumber=8576622","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T05:39:11Z","timestamp":1694497151000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8576622\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":54,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2883923","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}