{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T14:26:05Z","timestamp":1774967165533,"version":"3.50.1"},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ReproNano","award":["WE 4853\/1-3"],"award-info":[{"award-number":["WE 4853\/1-3"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tvlsi.2018.2884646","type":"journal-article","created":{"date-parts":[[2018,12,18]],"date-time":"2018-12-18T19:52:48Z","timestamp":1545162768000},"page":"560-572","source":"Crossref","is-referenced-by-count":99,"title":["Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6522-5628","authenticated-orcid":false,"given":"Shubham","family":"Rai","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2972-438X","authenticated-orcid":false,"given":"Jens","family":"Trommer","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Raitza","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3814-0378","authenticated-orcid":false,"given":"Thomas","family":"Mikolajick","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9504-5671","authenticated-orcid":false,"given":"Walter M.","family":"Weber","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7125-1737","authenticated-orcid":false,"given":"Akash","family":"Kumar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"1","article-title":"An efficient manipulation package for biconditional binary decision diagrams","author":"amar\u00fa","year":"2014","journal-title":"Proc Conf Design Automat Test Eur Conf Exhib (DATE)"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509585"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572294"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.137"},{"key":"ref31","first-page":"1","article-title":"Advanced system on a chip design based on controllable-polarity FETs","author":"gaillardon","year":"2014","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2014.2333675"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2460377"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593158"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488886"},{"key":"ref34","first-page":"338","article-title":"Exploiting transistor-level reconfiguration to optimize combinational circuits","author":"raitza","year":"2017","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.907835"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.107"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2765491.2765504"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2600347"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2010.2096437"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2006.307728"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1002\/pssr.201307247"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065681"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevLett.107.216807"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2014.06.010"},{"key":"ref26","first-page":"1","article-title":"Efficient arithmetic logic gates using double-gate silicon nanowire FETs","author":"amar\u00fa","year":"2013","journal-title":"IEEE 11th Int New Circuits and Syst C (NEWCAS)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2017.8053723"},{"key":"ref50","first-page":"767","article-title":"Technology mapping flow for emerging reconfigurable silicon nanowire transistors","author":"rai","year":"2018","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref51","article-title":"Toward more accurate scaling estimates of CMOS circuits from 180 nm to 22 nm","author":"stillmaker","year":"2011"},{"key":"ref53","first-page":"2111","article-title":"Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs","author":"zhang","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2358884"},{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1038\/srep45556","article-title":"Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs","volume":"7","author":"resta","year":"2017","journal-title":"Sci Rep"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1021\/acsnano.8b02739"},{"key":"ref40","author":"sutherland","year":"1999","journal-title":"Logical Effort Designing Fast CMOS Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2694969"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2018.8442159"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1021\/nl401826u"},{"key":"ref15","first-page":"169","article-title":"Reconfigurable nanowire transistors with multiple independent gates for efficient and programmable combinational circuits","author":"trommer","year":"2016","journal-title":"Proc Design Automation Test Eur Conf Exhibit"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3243472"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2015.2429893"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1021\/acsnano.6b07531"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1038\/srep29448","article-title":"Polarity control in WSe2 double-gate transistors","volume":"6","author":"resta","year":"2016","journal-title":"Sci Rep"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2017.2756040"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2014.2359112"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1021\/nl203094h"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1557\/opl.2014.110","article-title":"Material prospects of reconfigurable transistor (RFETs)&#x2014;From silicon to germanium nanowires","volume":"1659","author":"trommer","year":"2014","journal-title":"MRS Online Proceedings Library"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479004"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1063\/1.3280042"},{"key":"ref46","first-page":"605","article-title":"A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs","author":"rai","year":"2018","journal-title":"Proc Design Automation Test Eur Conf Exhibit"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2013.2290555"},{"key":"ref48","volume":"180","author":"brown","year":"2012","journal-title":"Field-Programmable Gate Arrays"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1016\/S1383-7621(00)00027-8"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1021\/acsnano.6b07531"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2014.2363386"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2018.2821638"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DRC.2017.7999426"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8649697\/08580544.pdf?arnumber=8580544","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:10:23Z","timestamp":1657746623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8580544\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":53,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2884646","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}