{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:12:26Z","timestamp":1742386346833,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Ministry of Higher Education and Scientific Research of Tunisia within the framework of the Tunisian\u2013Portuguese Cooperation Project in the field of scientific research and technology"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tvlsi.2018.2885407","type":"journal-article","created":{"date-parts":[[2018,12,25]],"date-time":"2018-12-25T19:41:36Z","timestamp":1545766896000},"page":"691-699","source":"Crossref","is-referenced-by-count":7,"title":["Mixed-Signal Overclocked I\/O Buffers Model Abstraction for Signal Integrity Assessment"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1777-2213","authenticated-orcid":false,"given":"Wael","family":"Dghais","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Malek","family":"Souilem","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Muhammad","family":"Alam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SaPIW.2015.7237385"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2016.2602212"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2015.0368"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488811"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742898"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2012.2234212"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LICS.1996.561342"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1007\/978-3-540-30494-4_3","article-title":"Verification of analog and mixed-signal circuits using hybrid system techniques","volume":"3312","author":"dang","year":"2004","journal-title":"Proc Int Conf Formal Methods Comput -Aided Design (FMCAD)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722281"},{"key":"ref19","first-page":"224","article-title":"A mixed-domain behavioral model&#x2019;s extraction for digital I\/O buffers","author":"dghais","year":"2012","journal-title":"Proc IEEE Conf Electr Performance Electron Packag Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.825475"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2013.2260861"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SaPIW.2016.7496307"},{"journal-title":"I\/O Buffer Information Specification Version 5 1","year":"2012","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2008.2004995"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2005.848396"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2007.4529731"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045116"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2011.2138704"},{"journal-title":"Control of Dead-Time Processes","year":"2007","author":"normey-rico","key":"ref20"},{"journal-title":"Advanced Design System User-Defined Models","year":"2005","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/INMMIC.2010.5480124"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8649697\/08588389.pdf?arnumber=8588389","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:10:23Z","timestamp":1657746623000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8588389\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":22,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2885407","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}