{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T04:23:33Z","timestamp":1772771013320,"version":"3.50.1"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"DST-SERB\u2014Early Career Research Award","award":["ECR\/2015\/000148"],"award-info":[{"award-number":["ECR\/2015\/000148"]}]},{"DOI":"10.13039\/100007845","name":"Ministry of Communication and Information Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007845","id-type":"DOI","asserted-by":"publisher"}]},{"name":"MeitY SMDP-C2S program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/tvlsi.2018.2886357","type":"journal-article","created":{"date-parts":[[2018,12,28]],"date-time":"2018-12-28T19:50:56Z","timestamp":1546026656000},"page":"1124-1137","source":"Crossref","is-referenced-by-count":17,"title":["Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9534-8808","authenticated-orcid":false,"given":"Swati","family":"Bhardwaj","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9355-0527","authenticated-orcid":false,"given":"Shashank","family":"Raghuraman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5636-0676","authenticated-orcid":false,"given":"Amit","family":"Acharyya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"crossref","first-page":"215e","DOI":"10.1161\/01.CIR.101.23.e215","article-title":"Physiobank, physiotoolkit, and physionet","volume":"101","author":"goldberger","year":"2000","journal-title":"Circulation"},{"key":"ref38","year":"2018","journal-title":"The Fastica Package for Matlab"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1959.5222693"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ICGCS.2010.5543095"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2017.8110000"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ECCTD.2017.8093246"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1986.1169138"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2445855"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/79.143467"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1478786.1478840"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EMBC.2015.7319951"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2015386"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNSRE.2015.2454503"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2633543"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JBHI.2016.2532354"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2002.804287"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2007.910555"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LSP.2016.2583658"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2008.4408442"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s11517-007-0268-9"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.813829"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(95)00016-X"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/0165-1684(94)90029-9"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/12.241595"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S0893-6080(00)00026-5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2014.2318592"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2011.2150219"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2007.915115"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"1809","DOI":"10.1109\/TNN.2011.2166979","article-title":"Energy-efficient FastICA implementation for biomedical signal separation","volume":"22","author":"van","year":"2011","journal-title":"IEEE Trans Neural Netw"},{"key":"ref7","first-page":"2","article-title":"Low complexity single channel ICA architecture design methodology for low power healthcare applications","volume":"3","author":"bhardwaj","year":"2017","journal-title":"IEEE Comput Soc VLSI Circuits Syst Lett"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1995.7.6.1129"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/10.841330"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2006.875991"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TGRS.2006.874135"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2000.911207"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.bspc.2014.09.009"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1111\/j.1469-8986.2010.01015.x"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2010.2090523"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/72.761722"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2009.5336227"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.7.1483"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1049\/el:19700212"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001939"},{"key":"ref43","author":"hwang","year":"1979","journal-title":"Computer Arithmetic Principles Architecture and Design"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2006.880980"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8698469\/08595443.pdf?arnumber=8595443","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:47:45Z","timestamp":1657745265000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8595443\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":45,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2886357","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,5]]}}}