{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T09:13:58Z","timestamp":1775121238532,"version":"3.50.1"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/tvlsi.2018.2888625","type":"journal-article","created":{"date-parts":[[2019,1,4]],"date-time":"2019-01-04T19:51:20Z","timestamp":1546631480000},"page":"524-534","source":"Crossref","is-referenced-by-count":12,"title":["A Full Digital Fractional-<inline-formula> <tex-math notation=\"LaTeX\">$N$ <\/tex-math> <\/inline-formula> TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4427-8066","authenticated-orcid":false,"given":"Liming","family":"Xiu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangye","family":"Wei","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3449-7305","authenticated-orcid":false,"given":"Yuhai","family":"Ma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"637","DOI":"10.1109\/TVLSI.2002.801607","article-title":"A ‘flying-adder’ architecture of frequency and phase synthesis with scalability","volume":"10","author":"xiu","year":"2002","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2223931"},{"key":"ref12","year":"2013","journal-title":"TMS320DM816x DaVinci Digital Media Processors Technical Reference Manual"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1002\/9781118347959"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/el:19750415"},{"key":"ref15","doi-asserted-by":"crossref","DOI":"10.1002\/9781119102175","author":"xiu","year":"2015","journal-title":"From Frequency to Time-Average-Frequency A Paradigm Shift in the Design of Electronic System"},{"key":"ref16","year":"2016","journal-title":"KC705 Evaluation Board for the Kintex-7 FPGA User Guide UG810 (v1 5)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2407370"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2470545"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2013.2240092"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/82.938354"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2011.2114897"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2018.2810602"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2008.928421"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2046237"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2024985"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857417"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.845187"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2015.2459051"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2180448"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2017.2689519"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8649697\/08602454.pdf?arnumber=8602454","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T17:59:25Z","timestamp":1694541565000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8602454\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":22,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2888625","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,3]]}}}