{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:11Z","timestamp":1740133271051,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft","doi-asserted-by":"publisher","award":["276397488"],"award-info":[{"award-number":["276397488"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/tvlsi.2018.2890601","type":"journal-article","created":{"date-parts":[[2019,1,18]],"date-time":"2019-01-18T19:38:55Z","timestamp":1547840335000},"page":"875-887","source":"Crossref","is-referenced-by-count":8,"title":["Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6950-7967","authenticated-orcid":false,"given":"Sebastian","family":"Huhn","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Frehse","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4993-7860","authenticated-orcid":false,"given":"Robert","family":"Wille","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45069-6_1"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/11560548_12"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358110"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2044673"},{"key":"ref31","first-page":"4","article-title":"Efficient circuit to CNF conversion","author":"manolios","year":"2007","journal-title":"Theory and Applications of Satisfiability Testing"},{"key":"ref30","first-page":"466","volume":"8","author":"tseitin","year":"1983","journal-title":"On the Complexity of Derivations in Prepositional Calculus"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313303"},{"key":"ref36","first-page":"317","article-title":"Symbolic model checking using sat procedures instead of BDDs","author":"biere","year":"1999","journal-title":"Proc Design Automat Conf"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/302405.302672"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.170"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858317"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480006"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.21236\/ADA360973"},{"key":"ref12","first-page":"502","article-title":"An extensible SAT-solver","author":"e\u00e9n","year":"2003","journal-title":"Proc Int Conf Theory Appl Satisfiability Test"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2006.42"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2005.853449"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.244062"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2010.26"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2120950"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479838"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1147\/rd.104.0278"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1950.tb00463.x"},{"key":"ref27","first-page":"85","article-title":"Improved SAT-based ATPG: More constraints, better compaction","author":"eggersgl\u00fc\u00df","year":"2013","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LICS.1989.39193"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref29","volume":"185","author":"biere","year":"2009","journal-title":"Handbook of Satisfiability"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TDMR.2012.2204753"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ARES.2008.199"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523226"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1989.82370"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2241176"},{"journal-title":"Fault-Tolerance Techniques for SRAM-based FPGAs","year":"2006","author":"kastensmidt","key":"ref1"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2009.5012096"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277207"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2011.34"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-75596-8_13"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061131"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1002\/0471457787"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.823342"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766649"},{"key":"ref44","first-page":"21","author":"grumberg","year":"2009","journal-title":"3-Valued Abstraction for (Bounded) Model Checking"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-2360-5"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1007\/s10009-016-0426-1"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/43.108614"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8672976\/08618608.pdf?arnumber=8618608","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:14:23Z","timestamp":1657746863000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8618608\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":46,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2018.2890601","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,4]]}}}