{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T15:04:34Z","timestamp":1761663874823,"version":"3.37.3"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T00:00:00Z","timestamp":1556668800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Brazilian funding agencies CAPES"},{"DOI":"10.13039\/501100003593","name":"Conselho Nacional de Desenvolvimento Cient\u00edfico e Tecnol\u00f3gico","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003593","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004263","name":"FAPERGS","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004263","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,5]]},"DOI":"10.1109\/tvlsi.2019.2890843","type":"journal-article","created":{"date-parts":[[2019,1,23]],"date-time":"2019-01-23T00:03:09Z","timestamp":1548201789000},"page":"1228-1232","source":"Crossref","is-referenced-by-count":9,"title":["Four-Level Forms for Memristive Material Implication Logic"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5368-6750","authenticated-orcid":false,"given":"Felipe S.","family":"Marranghello","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vinicius","family":"Callegaro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3118-8160","authenticated-orcid":false,"given":"Andre I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9895-7489","authenticated-orcid":false,"given":"Renato P.","family":"Ribas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2729499"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.3407"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2014.7001393"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2269799"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2187524"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2426511"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357108"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2695880"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482461"},{"key":"ref19","first-page":"225","article-title":"SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic","author":"hur","year":"2017","journal-title":"Proc 36th Int Conf Comput -Aided Design (ICCAD)"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2018.2803117"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s12274-016-1260-1"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6528\/aacf84"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1038\/nature08940"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1088\/0957-4484\/23\/30\/305205"},{"journal-title":"IEEE Trans Emerg Topics Comput","year":"0","author":"maestro","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2551554"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2017.2691713"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2433311"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1063\/1.1702530"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2792474"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/srep13330"},{"journal-title":"Introduction to Graph Theory","year":"2001","author":"west","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2572726"},{"journal-title":"Integr VLSI J","year":"0","author":"yang","key":"ref26"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2015.2481439"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8698469\/08621037.pdf?arnumber=8621037","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:47:45Z","timestamp":1657745265000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8621037\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,5]]},"references-count":28,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2890843","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,5]]}}}