{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:26:56Z","timestamp":1766269616030,"version":"3.37.3"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000780","name":"European Commission","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000780","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ANR\/DFG as part of the MASTA Project"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1109\/tvlsi.2019.2904197","type":"journal-article","created":{"date-parts":[[2019,3,26]],"date-time":"2019-03-26T23:11:08Z","timestamp":1553641868000},"page":"1697-1710","source":"Crossref","is-referenced-by-count":14,"title":["A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1177-8291","authenticated-orcid":false,"given":"Sarath Mohanachandran","family":"Nair","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0516-7112","authenticated-orcid":false,"given":"Rajendra","family":"Bishnoi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehdi B.","family":"Tahoori","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342114"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2016.2541629"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2463585.2463589"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2198825"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.3390\/ma9010041"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2412960"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1018"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2064150"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2749522"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391540"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2015.7357091"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2043694"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775920"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547779"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035342"},{"key":"ref17","first-page":"54","article-title":"STTRAM scaling and retention failure","volume":"17","author":"naeimi","year":"2013","journal-title":"Intel Technology Journal"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297306"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2014.2374291"},{"key":"ref28","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927049"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/S1369-7021(06)71539-5"},{"key":"ref6","first-page":"731","article-title":"An overview of non-volatile memory technology and the implication for tools and architectures","author":"li","year":"2009","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011170"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.97"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.24"},{"key":"ref7","first-page":"143","article-title":"Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM","author":"chang","year":"2013","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit (HPCA)"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"2013","author":"wilson","key":"ref2"},{"key":"ref9","article-title":"STT-RAM&#x2014;A new spin on universal memory","author":"smith","year":"2008","journal-title":"Future Fab International Report"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2619484"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342016"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"ref42","first-page":"1","article-title":"SPITT: A magnetic tunnel junction SPICE compact model for STT-MRAM","author":"granger","year":"2015","journal-title":"Proc MOS-AK Workshop Design Autom Test Eur"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/MIEL.2012.6222840"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-018-03140-z"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2630315"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2760861"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8746725\/08674834.pdf?arnumber=8674834","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:53:56Z","timestamp":1657745636000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8674834\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7]]},"references-count":42,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2904197","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,7]]}}}