{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,20]],"date-time":"2025-12-20T22:31:33Z","timestamp":1766269893695,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,9,1]],"date-time":"2019-09-01T00:00:00Z","timestamp":1567296000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"CONACYT (Mexico) through the Ph.D. Scholarship","award":["434673\/294398"],"award-info":[{"award-number":["434673\/294398"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,9]]},"DOI":"10.1109\/tvlsi.2019.2918768","type":"journal-article","created":{"date-parts":[[2019,7,7]],"date-time":"2019-07-07T16:55:41Z","timestamp":1562518541000},"page":"2180-2190","source":"Crossref","is-referenced-by-count":16,"title":["Modeling and Detectability of Full Open Gate Defects in FinFET Technology"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9939-0974","authenticated-orcid":false,"given":"Freddy","family":"Forero","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4405-4935","authenticated-orcid":false,"given":"Hector","family":"Villacorta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3896-8231","authenticated-orcid":false,"given":"Michel","family":"Renovell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4440-3800","authenticated-orcid":false,"given":"Victor","family":"Champac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"29.1.1","article-title":"A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects","author":"auth","year":"2017","journal-title":"IEDM Tech Dig"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(98)00105-X"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2015.7409744"},{"key":"ref30","first-page":"2d.1.1","article-title":"Technology scaling on high-\n$\\kappa$\n & metal-gate FinFET BTI reliability","author":"lee","year":"2013","journal-title":"Proc IEEE Int Rel Phys Symp (IRPS)"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1996.510888"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2205609"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2648843"},{"journal-title":"Predictive Technology Model (PTM)","year":"2019","key":"ref13"},{"key":"ref14","first-page":"3.7.1","article-title":"A 14 nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 \n$\\mu\\text{m}^{2}$\nSRAM cell size","author":"natarajan","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531970"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2063191"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2009.09.015"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2032605"},{"key":"ref19","first-page":"1","article-title":"Optimization of STI oxide recess uniformity for FinFET beyond 20 nm","author":"du","year":"2015","journal-title":"Proc China Semicond Technol Int Conf"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2423634"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401565"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884403"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169807"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-SoC.2017.8203483"},{"journal-title":"Applied Statistics and Probability for Engineers","year":"2010","author":"montgomery","key":"ref29"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-017-5674-9"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741618"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.265677"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2015.7114547"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2397934"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.881001"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.39"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1631\/jzus.C1100242"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2012.2199499"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805769"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2008.05.034"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-75465-9"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2010.5551437"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8811586\/08753549.pdf?arnumber=8753549","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:06:16Z","timestamp":1657746376000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8753549\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,9]]},"references-count":33,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2918768","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,9]]}}}