{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,19]],"date-time":"2025-06-19T05:29:03Z","timestamp":1750310943773,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/tvlsi.2019.2924686","type":"journal-article","created":{"date-parts":[[2019,7,12]],"date-time":"2019-07-12T20:09:45Z","timestamp":1562962185000},"page":"2575-2586","source":"Crossref","is-referenced-by-count":9,"title":["Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5640-2250","authenticated-orcid":false,"given":"Kentaro","family":"Yoshioka","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tetsuro","family":"Itakura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomohiko","family":"Sugimoto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Naoya","family":"Waki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sinnyoung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daisuke","family":"Kurose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hirotomo","family":"Ishii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masanori","family":"Furuta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0440-1672","authenticated-orcid":false,"given":"Akihide","family":"Sai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hiroki","family":"Ishikuro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"ADC Performance Survey 1997-2018","year":"2018","author":"murmann","key":"ref32"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942109"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487731"},{"key":"ref10","first-page":"204","article-title":"11.6 A 21mW 15b 48MS\/s zero-crossing pipeline ADC in \n$0.13~\\mu\\text{m}$\n CMOS with 74dB SNDR","author":"chang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217865"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2463094"},{"article-title":"Ring amplification for switched capacitor circuits","year":"2012","author":"hershberg","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234320"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858451"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref17","first-page":"268c","article-title":"A 2.1 mW 11b 410 MS\/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS","author":"verbruggen","year":"2013","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742523"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708780"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126390"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2387849"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2591822"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523296"},{"key":"ref29","first-page":"270","article-title":"A 2.2\/2.7 fJ\/conversion-step 10\/12b 40kS\/s SAR ADC with data-driven noise reduction","author":"harpe","year":"2013","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref8","first-page":"166","article-title":"A 12b 50MS\/s fully differential zero-crossing-based ADC without CMFB","author":"brooks","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884330"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231330"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032639"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MWC.2016.7422404"},{"key":"ref20","first-page":"478","article-title":"28.7 A 0.7 V 12b 160MS\/s 12.8 fJ\/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique","author":"yoshioka","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","first-page":"542","article-title":"A 32mW 1.25 GS\/s 6b 2b\/step SAR ADC in \n$0.13~\\mu\\text{m}$\n CMOS","author":"cao","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217872"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2304733"},{"key":"ref26","first-page":"196","article-title":"11.2 A 0.85 fJ\/conversion-step 10b 200kS\/s subranging SAR ADC in 40nm CMOS","author":"tai","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","first-page":"1","article-title":"Settling time of operational amplifiers","volume":"4","author":"demerow","year":"1970","journal-title":"Analog Dialogue"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8880704\/08760584.pdf?arnumber=8760584","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:49:18Z","timestamp":1657745358000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8760584\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":32,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2924686","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}