{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T17:37:53Z","timestamp":1774028273780,"version":"3.50.1"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/tvlsi.2019.2925820","type":"journal-article","created":{"date-parts":[[2019,7,18]],"date-time":"2019-07-18T19:58:52Z","timestamp":1563479932000},"page":"2698-2702","source":"Crossref","is-referenced-by-count":8,"title":["A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor"],"prefix":"10.1109","volume":"27","author":[{"given":"Yu-Kai","family":"Chiu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3765-2948","authenticated-orcid":false,"given":"Shen-Iuan","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638432"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2844331"},{"key":"ref12","first-page":"118","article-title":"A 0.0056 mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3 mW block-sharing frequency tracking loop achieving 292fs\n$\\rm_{rms}$\n jitter and ?249 dB FOM","author":"yang","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2598768"},{"key":"ref4","first-page":"1","article-title":"A PVT-robust&#x2013;59-dBc reference spur and 450-fs RMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop","author":"lee","year":"2016","journal-title":"Proc IEEE Symp VLSI Circuits (VLSI)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2574804"},{"key":"ref6","first-page":"466","article-title":"A 4.6GHz MDLL with ?46dBc reference spur and aperture position tuning","author":"ali","year":"2011","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"78","article-title":"A multiple-crystal interface PLL with VCO realignment to reduce phase noise","author":"ye","year":"2002","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917372"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2227609"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2734910"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8880704\/08765773.pdf?arnumber=8765773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:49:19Z","timestamp":1657745359000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8765773\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":13,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2925820","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,11]]}}}