{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,26]],"date-time":"2026-03-26T02:19:25Z","timestamp":1774491565632,"version":"3.50.1"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,10,1]],"date-time":"2019-10-01T00:00:00Z","timestamp":1569888000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002183","name":"Department of Electronics and Information Technology, Ministry of Communications and Information Technology","doi-asserted-by":"publisher","award":["VISPHD-MEITY-1699"],"award-info":[{"award-number":["VISPHD-MEITY-1699"]}],"id":[{"id":"10.13039\/501100002183","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,10]]},"DOI":"10.1109\/tvlsi.2019.2926788","type":"journal-article","created":{"date-parts":[[2019,7,29]],"date-time":"2019-07-29T19:25:33Z","timestamp":1564428333000},"page":"2284-2295","source":"Crossref","is-referenced-by-count":13,"title":["Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3752-3895","authenticated-orcid":false,"given":"J.","family":"Kokila","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Ramasubramanian","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nagi","family":"Naganathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1049\/el.2018.0735"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2018.2870835"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5209-8"},{"key":"ref32","first-page":"381","article-title":"Light weight two-factor authentication using hybrid PUF and FSM for SOC FPGA","author":"kokila","year":"2017","journal-title":"Proc Int Conf Next Gener Comput Technol"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2098131"},{"key":"ref30","first-page":"347","article-title":"PUFs at a glance","author":"r\u00fchrmair","year":"2014","journal-title":"Proc of the Conf on Design Automation and Test in Europe Euro Design and Automation Ass"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2013.2279798"},{"key":"ref36","first-page":"349","article-title":"Hybrid side-channel\/machine-learning attacks on PUFs: A new threat?","author":"xiaolin","year":"2014","journal-title":"Proc Conf Design Automation Test Eur"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2014.2300635"},{"key":"ref34","first-page":"116","article-title":"Silicon Physical Unclonable Function resistant to a 1025-trial brute force attack in 90 nm CMOS","author":"stanzione","year":"2009","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MobileCloud.2017.35"},{"key":"ref40","article-title":"Securing embedded digital systems for in-field applications","author":"barbareschi","year":"2014"},{"key":"ref11","article-title":"Reliable, secure, efficient physical unclonable functions","author":"bhargava","year":"2013"},{"key":"ref12","article-title":"Secure and lightweight hardware authentication using isolated physical unclonable function","author":"shahrak","year":"2016"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MMSP.2016.7813398"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378632"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"9","DOI":"10.1145\/1278480.1278484","article-title":"physical unclonable functions for device authentication and secret key generation","author":"suh","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-85053-3_12"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2569581"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2968455.2968519"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-48324-4_28"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2013.28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2016.2606384"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8080-9_5"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.3711654"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050602"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2169667"},{"key":"ref5","year":"2017","journal-title":"IoT Edge SoC Platform Open-Silicon"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2017.2703088"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2320516"},{"key":"ref2","first-page":"1776","article-title":"Dynamic estimation of temporary failure in SoC FPGAs for heterogeneous applications","volume":"24","author":"kokila","year":"2018","journal-title":"J Universal Comput Sci"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.future.2018.01.059"},{"key":"ref1","year":"2017","journal-title":"What is an SoC FPGA?"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RFID-TA.2010.5529941"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2355043"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2013.6573635"},{"key":"ref42","article-title":"Design and evaluation of FPGA-based hybrid physically unclonable functions","author":"khoshroo","year":"2013"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2619682"},{"key":"ref41","doi-asserted-by":"crossref","first-page":"1143","DOI":"10.1109\/TCAD.2015.2424955","article-title":"A low-power hybrid RO PUF with improved thermal stability for lightweight applications","volume":"34","author":"cao","year":"2015","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2015.2455338"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2017.2767291"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2015.2400413"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2163307"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2282282"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8848667\/08779595.pdf?arnumber=8779595","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:14:23Z","timestamp":1657746863000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8779595\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,10]]},"references-count":44,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2926788","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,10]]}}}