{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T22:30:50Z","timestamp":1773873050814,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,12,1]],"date-time":"2019-12-01T00:00:00Z","timestamp":1575158400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1408123"],"award-info":[{"award-number":["CCF-1408123"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1438286"],"award-info":[{"award-number":["CCF-1438286"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2019,12]]},"DOI":"10.1109\/tvlsi.2019.2929354","type":"journal-article","created":{"date-parts":[[2019,8,9]],"date-time":"2019-08-09T20:00:53Z","timestamp":1565380853000},"page":"2925-2938","source":"Crossref","is-referenced-by-count":77,"title":["Performing Stochastic Computation Deterministically"],"prefix":"10.1109","volume":"27","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4655-6229","authenticated-orcid":false,"given":"M. Hassan","family":"Najafi","sequence":"first","affiliation":[]},{"given":"Devon","family":"Jenson","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3785-8206","authenticated-orcid":false,"given":"David J.","family":"Lilja","sequence":"additional","affiliation":[]},{"given":"Marc D.","family":"Riedel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Digital yet deliberately random: Synthesizing logical computation on stochastic bit streams","author":"qian","year":"2011"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2645902"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.4241345"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580163"},{"key":"ref14","first-page":"76","article-title":"Fast and accurate computation using stochastic circuits","author":"alaghi","year":"2014","journal-title":"Proc Conf Design Automat Test Eur"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927069"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2812214"},{"key":"ref17","first-page":"1757","article-title":"Energy-efficient convolutional neural networks with deterministic bit-stream processing","author":"faraji","year":"2019","journal-title":"Proc Conf Design Autom Test Eur (DATE)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488901"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.202"},{"key":"ref3","first-page":"1","article-title":"Synthesizing logical computation on stochastic bit streams","author":"qian","year":"2009","journal-title":"Proc DAC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TSP.2010.2051434"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2465787.2465794"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/29.1564"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2778107"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/12.954505"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4899-5841-9_2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1137\/1.9781611970081"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/8910476\/8793244-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8910476\/08793244.pdf?arnumber=8793244","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T21:06:17Z","timestamp":1657746377000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8793244\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,12]]},"references-count":18,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2929354","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2019,12]]}}}