{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:18Z","timestamp":1740133278523,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,1]]},"DOI":"10.1109\/tvlsi.2019.2943073","type":"journal-article","created":{"date-parts":[[2019,10,15]],"date-time":"2019-10-15T22:14:01Z","timestamp":1571177641000},"page":"287-291","source":"Crossref","is-referenced-by-count":4,"title":["RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory"],"prefix":"10.1109","volume":"28","author":[{"given":"Morteza","family":"Soltani","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7098-6440","authenticated-orcid":false,"given":"Mehdi","family":"Kamal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8614-2007","authenticated-orcid":false,"given":"Ali","family":"Afzali-Kusha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2677-7307","authenticated-orcid":false,"given":"Massoud","family":"Pedram","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.2295825"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2479593"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2018.2861012"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749753"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2000064.2000086"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2642180"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669157"},{"key":"ref17","first-page":"169","article-title":"53 Gbps native GF (24)2 composite-field AES-encrypt\/decrypt accelerator for content-protection in 45 nm high-performance microprocessors","author":"mathew","year":"2010","journal-title":"Proc VLSI Circuits (VLSIC) Symp"},{"journal-title":"Improved security for non volatile main memory","year":"2017","author":"haber","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2012.6378664"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2016.07.006"},{"key":"ref3","first-page":"1116","article-title":"The RowHammer problem and other issues we may face as memory becomes denser","author":"mutlu","year":"2017","journal-title":"Proc Conf Design Autom Test Eur"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.46"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2015.7363650"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2006.354942"},{"key":"ref2","first-page":"1","article-title":"Architecting for power management: The IBM power7 approach","author":"ware","year":"2010","journal-title":"Proc High Perform Comput Archit (HPCA)"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"267","DOI":"10.1145\/1555815.1555789","article-title":"Disaggregated memory for expansion and sharing in blade servers","volume":"37","author":"lim","year":"2009","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1816038.1815980"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2902961.2902980"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1186736.1186737","article-title":"SPEC CPU2006 benchmark descriptions","volume":"34","author":"henning","year":"2006","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2503210.2503215"},{"journal-title":"NanGate—The Standard Cell Library Optimization Company","year":"2016","key":"ref23"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8945454\/08870250.pdf?arnumber=8870250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:04Z","timestamp":1651070404000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8870250\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1]]},"references-count":24,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2943073","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,1]]}}}