{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:19Z","timestamp":1740133279083,"version":"3.37.3"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,2,1]],"date-time":"2020-02-01T00:00:00Z","timestamp":1580515200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"European Union\u2019s Horizon 2020 Research and Innovation Program","award":["739551"],"award-info":[{"award-number":["739551"]}]},{"name":"Republic of Cyprus through the Directorate General for European Programs, Coordination and Development"},{"DOI":"10.13039\/100010661","name":"Horizon 2020 Framework Programme","doi-asserted-by":"publisher","award":["10.13039\/100010661"],"award-info":[{"award-number":["10.13039\/100010661"]}],"id":[{"id":"10.13039\/100010661","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,2]]},"DOI":"10.1109\/tvlsi.2019.2947183","type":"journal-article","created":{"date-parts":[[2019,10,29]],"date-time":"2019-10-29T20:00:28Z","timestamp":1572379228000},"page":"553-564","source":"Crossref","is-referenced-by-count":0,"title":["Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9029-2101","authenticated-orcid":false,"given":"Stavros","family":"Hadjitheophanous","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5728-6845","authenticated-orcid":false,"given":"Stelios N.","family":"Neophytou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1943-6547","authenticated-orcid":false,"given":"Maria K.","family":"Michael","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651913"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699236"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651916"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2014.7035349"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0077"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2158432"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488769"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847835"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-018-5747-4"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894222"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2855131"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.506139"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1989.82360"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2157693"},{"key":"ref29","volume":"17","author":"bushnell","year":"2004","journal-title":"Essentials of Electronic Testing for Digital Memory and Mixed-Signal VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.20"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2018.2833059"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-03095-6_35"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847807"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742967"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2015.7138738"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966652"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2102056"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437649"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090833"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1109\/TCAD.2011.2168526","article-title":"Physically-aware n-detect test","volume":"31","author":"lin","year":"2012","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/AQTR.2018.8402703"},{"article-title":"Failure evasion: Statistically solving the NP complete problem of testing difficult-to-detect faults","year":"2016","author":"venkatasubramanian","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/8964612\/08886719.pdf?arnumber=8886719","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:25Z","timestamp":1651070425000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8886719\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,2]]},"references-count":29,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2947183","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,2]]}}}