{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,24]],"date-time":"2025-06-24T06:28:39Z","timestamp":1750746519615,"version":"3.37.3"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003621","name":"Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["2019R1A2C3011079"],"award-info":[{"award-number":["2019R1A2C3011079"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/tvlsi.2019.2954549","type":"journal-article","created":{"date-parts":[[2019,12,17]],"date-time":"2019-12-17T21:11:17Z","timestamp":1576617077000},"page":"805-817","source":"Crossref","is-referenced-by-count":9,"title":["GPU-Based Redundancy Analysis Using Concurrent Evaluation"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2619-0637","authenticated-orcid":false,"given":"Tae Hyun","family":"Kim","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6868-0829","authenticated-orcid":false,"given":"Hayoung","family":"Lee","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7093-2095","authenticated-orcid":false,"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","first-page":"33","article-title":"RAMSES-D: DRAM fault simulator supporting weighted coupling fault","author":"hsing","year":"2007","journal-title":"Proc IEEE Int Workshop Memory Technol Design Test"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2760505"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2044846"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.10.0210.0032"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2606499"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2752298"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2017.2778301"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2818725"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/92.285750"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294737"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/66.97808"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1982.1051831"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586118"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250090"},{"key":"ref5","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"tarr","year":"1984","journal-title":"Electronics"},{"key":"ref8","first-page":"478","article-title":"A fast redundancy analysis algorithm in ATE for repairing faulty memories","volume":"34","author":"cho","year":"2012","journal-title":"ETRI J"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2006.874942"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1981.1051630"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0112.0467"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1979.19509"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2004.01.013"},{"journal-title":"CUDA by Example An Introduction to General-Purpose GPU Programming","year":"2010","author":"sanders","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISBI.2008.4541126"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.cpc.2015.02.028"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2788396"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"},{"journal-title":"Programming Massively Parallel Processors A Hands-on Approach","year":"2016","author":"kirk","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9011687\/08935214.pdf?arnumber=8935214","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:14Z","timestamp":1651070414000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8935214\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":30,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2954549","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,3]]}}}