{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,12]],"date-time":"2026-05-12T08:40:44Z","timestamp":1778575244933,"version":"3.51.4"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,3,1]],"date-time":"2020-03-01T00:00:00Z","timestamp":1583020800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001413","name":"Indian Space Research Organisation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001413","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100005144","name":"Qualcomm","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005144","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,3]]},"DOI":"10.1109\/tvlsi.2019.2956100","type":"journal-article","created":{"date-parts":[[2019,12,19]],"date-time":"2019-12-19T20:53:59Z","timestamp":1576788839000},"page":"714-725","source":"Crossref","is-referenced-by-count":10,"title":["A Fast Settling Fractional-$N$  DPLL With Loop-Order Switching"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4821-5284","authenticated-orcid":false,"given":"Pallavi","family":"Paliwal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"Yadav","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zeeshan","family":"Ali","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5988-9420","authenticated-orcid":false,"given":"Shalabh","family":"Gupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2477575"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674757"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942026"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2016.7451049"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.889443"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACC.2003.1243434"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2011.2176957"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4612-0017-8"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2620151"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2625462"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2015.7313882"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2272340"},{"key":"ref4","first-page":"324","article-title":"A 0.5-to-9.5 GHz 1.2 \n$\\mu\\text{s}$\n-lock-time fractional-N DPLL with &#x00B1;1.25% UI period jitter in 16 nm CMOS for dynamic frequency and core-count scaling in SoC","author":"ahmad","year":"2016","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref3","first-page":"250","article-title":"A 36.3-to-38.2 GHz ?216dBc\/Hz2 40 nm CMOS fractional-N FMCW chirp synthesizer PLL with a continuous-time bandpass delta-sigma time-to-digital converter","author":"weyer","year":"2018","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2638882"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2702742"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2016.48"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922721"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref2","first-page":"408","article-title":"A self-calibrated 16 GHz subsampling-PLL-based 30s fast chirp FMCW modulator with 1.5 GHz Bandwidth and 100 kHz rms error","author":"shi","year":"2019","journal-title":"IEEE ISSCC Dig Tech Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2017.8094573"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310277"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2196313"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2011.2172526"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2274892"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2014.7049912"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2560340"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9011687\/08937009.pdf?arnumber=8937009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:14Z","timestamp":1651070414000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8937009\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,3]]},"references-count":32,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2956100","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,3]]}}}