{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T20:13:42Z","timestamp":1761596022331,"version":"3.37.3"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003711","name":"Ministry of Science and Technology","doi-asserted-by":"publisher","award":["MOST 107-2221-E-011-110"],"award-info":[{"award-number":["MOST 107-2221-E-011-110"]}],"id":[{"id":"10.13039\/501100003711","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100007530","name":"National Taiwan University of Science and Technology","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100007530","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100007780","name":"Kyushu Institute of Technology","doi-asserted-by":"publisher","award":["Kyutech-NTUST-106-02"],"award-info":[{"award-number":["Kyutech-NTUST-106-02"]}],"id":[{"id":"10.13039\/501100007780","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tvlsi.2019.2962606","type":"journal-article","created":{"date-parts":[[2020,1,14]],"date-time":"2020-01-14T21:17:09Z","timestamp":1579036629000},"page":"904-913","source":"Crossref","is-referenced-by-count":19,"title":["High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0749-4181","authenticated-orcid":false,"given":"Poki","family":"Chen","sequence":"first","affiliation":[]},{"given":"Jian-Ting","family":"Lan","sequence":"additional","affiliation":[]},{"given":"Ruei-Ting","family":"Wang","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6044-1778","authenticated-orcid":false,"given":"Nguyen","family":"My Qui","sequence":"additional","affiliation":[]},{"given":"John Carl Joel S.","family":"Marquez","sequence":"additional","affiliation":[]},{"given":"Seiji","family":"Kajihara","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6742-5105","authenticated-orcid":false,"given":"Yousuke","family":"Miyake","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1063\/1.1683667"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2015.2389227"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/4.508208"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/4.826814"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/6144.868863"},{"volume":"4","journal-title":"Stratix IV Device Handbook Device Datasheet and Addendum","year":"2014","key":"ref34"},{"key":"ref10","first-page":"347","article-title":"Multi-stage pulse shrinking time-to-digital converter for time interval measurements","author":"liu","year":"2007","journal-title":"Proc Eur Microw Integr Circuit Conf"},{"key":"ref11","first-page":"2776","article-title":"A low-noise wide-BW 3.6-GHz digital \n$\\Delta\\Sigma$\n fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation","volume":"43","author":"perrott","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2017.8094546"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2016.7844198"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338425"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2013.6674777"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063035"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/NSSMIC.2008.4775079"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2421319"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2017.2769239"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2010.5512772"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2768082"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/I2MTC.2018.8409646"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231102"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2569626"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2012.6233035"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2011.2122510"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2016.7799706"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICEE.2018.8472459"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.874281"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/23.757192"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/RTC.2016.7543081"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2016.2534670"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2016.2606627"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2017.2663498"},{"key":"ref23","first-page":"1","article-title":"Multiple-event direct to histogram TDC in 65nm FPGA technology","author":"dutton","year":"2014","journal-title":"Proc Ph D Rese Microelectron Electron Conf (PRIME)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2426214"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2746626"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9043771\/08959406.pdf?arnumber=8959406","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:39:58Z","timestamp":1651070398000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8959406\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":36,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2019.2962606","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}