{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T09:19:26Z","timestamp":1773825566860,"version":"3.50.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100008982","name":"National Science Foundation","doi-asserted-by":"publisher","award":["1423290"],"award-info":[{"award-number":["1423290"]}],"id":[{"id":"10.13039\/501100008982","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/tvlsi.2020.2970041","type":"journal-article","created":{"date-parts":[[2020,2,20]],"date-time":"2020-02-20T22:30:17Z","timestamp":1582237817000},"page":"980-991","source":"Crossref","is-referenced-by-count":19,"title":["Approximate Memory Compression"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2434-0475","authenticated-orcid":false,"given":"Ashish","family":"Ranjan","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8848-1069","authenticated-orcid":false,"given":"Arnab","family":"Raha","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4713-5386","authenticated-orcid":false,"given":"Vijay","family":"Raghunathan","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","year":"2018","journal-title":"Everspin 256Mb DDR3 Spin-Torque MRAM (EMD3D256M08G1)"},{"key":"ref38","year":"2018","journal-title":"Micron EDF8164A1MA Datasheet"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref32","year":"2018","journal-title":"Everspin STT-MRAM"},{"key":"ref31","first-page":"449","article-title":"Hardware-assisted data compression for energy minimization in systems with embedded processors","author":"benini","year":"2003","journal-title":"Proc Design Autom Test Eur Conf Exhibition (DATE)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/43.811316"},{"key":"ref37","year":"2018","journal-title":"Micron MT41J512M8 Datasheet"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2012.82"},{"key":"ref34","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-031-01722-3","author":"barroso","year":"2009","journal-title":"The Datacenter as a Computer An Introduction to the Design of Warehouse-Scale Machines"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2016.2640296"},{"key":"ref40","year":"2015","journal-title":"Nios-II Processor"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428043"},{"key":"ref12","first-page":"1","article-title":"Sparkk: Quality-scalable approximate storage in DRAM","author":"lucas","year":"2014","journal-title":"Memory Forum Workshop"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627626"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2644808"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.22"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830790"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783744"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2393860"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783746"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.6"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540724"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2011.7477494"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488873"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775912"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917729"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2505723"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2751163"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382159"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.134"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2105550"},{"key":"ref22","first-page":"356","article-title":"STAxCache: An approximate, energy efficient STT-MRAM cache","author":"ranjan","year":"2017","journal-title":"Proc Eur Conf Exhib Design Autom Test"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744799"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009173"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.2200\/S00683ED1V01Y201511CAC036"},{"key":"ref41","year":"2013","journal-title":"Introduction to UniPHY IP"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009198"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1944862.1944876"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/40.918003"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/9043771\/9004534-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9043771\/09004534.pdf?arnumber=9004534","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,27]],"date-time":"2023-09-27T08:25:43Z","timestamp":1695803143000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9004534\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":42,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2970041","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,4]]}}}