{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T15:21:52Z","timestamp":1783610512448,"version":"3.55.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,5,1]],"date-time":"2020-05-01T00:00:00Z","timestamp":1588291200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Basic Research Program of China","doi-asserted-by":"publisher","award":["2018YFB2202602"],"award-info":[{"award-number":["2018YFB2202602"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"State Key Program of National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61934005"],"award-info":[{"award-number":["61934005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,5]]},"DOI":"10.1109\/tvlsi.2020.2976099","type":"journal-article","created":{"date-parts":[[2020,3,13]],"date-time":"2020-03-13T20:21:03Z","timestamp":1584130863000},"page":"1316-1320","source":"Crossref","is-referenced-by-count":62,"title":["In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3314-1606","authenticated-orcid":false,"given":"Zhiting","family":"Lin","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2840-9639","authenticated-orcid":false,"given":"Honglan","family":"Zhan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6009-7711","authenticated-orcid":false,"given":"Xuan","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2408-5048","authenticated-orcid":false,"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenjuan","family":"Lu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5012-2570","authenticated-orcid":false,"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCET.2019.8726871"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref10","article-title":"Research and realiztion of critical circuits for low-voltage static random access memory","author":"zhu","year":"2014"},{"key":"ref6","first-page":"160c","article-title":"A 0.3V VDDmin \n$4+2\\text{T}$\n SRAM for searching and in-memory computing using 55 nm DDC technology","author":"dong","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2016.2515510","article-title":"A 28 nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory","volume":"51","author":"jeloka","year":"2016","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2897497"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2929245"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649109"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2876785"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9078135\/09035462.pdf?arnumber=9035462","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:24Z","timestamp":1651070424000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9035462\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,5]]},"references-count":10,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2976099","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,5]]}}}