{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,22]],"date-time":"2026-07-22T16:24:32Z","timestamp":1784737472045,"version":"3.55.0"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1109\/tvlsi.2020.2982473","type":"journal-article","created":{"date-parts":[[2020,4,15]],"date-time":"2020-04-15T22:13:46Z","timestamp":1586988826000},"page":"1435-1448","source":"Crossref","is-referenced-by-count":27,"title":["Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations"],"prefix":"10.1109","volume":"28","author":[{"given":"Samaneh","family":"Ghandali","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3809-9803","authenticated-orcid":false,"given":"Thorben","family":"Moos","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4032-7433","authenticated-orcid":false,"given":"Amir","family":"Moradi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8681-2277","authenticated-orcid":false,"given":"Christof","family":"Paar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"142","article-title":"Fides: Lightweight authenticated cipher with side-channel resistance for constrained hardware","volume":"8086","author":"bilgin","year":"2013","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref38","first-page":"263","article-title":"Affine equivalence and its application to tightening threshold implementations","volume":"9566","author":"sasdrich","year":"2015","journal-title":"Proc Selected Areas Cryptography"},{"key":"ref33","first-page":"95","article-title":"An efficient side-channel protected AES implementation with arbitrary protection order","volume":"10159","author":"gross","year":"2017","journal-title":"Topics in Cryptology&#x2014;CT-RSA"},{"key":"ref32","first-page":"764","article-title":"Consolidating masking schemes","volume":"9215","author":"reparaz","year":"2015","journal-title":"Adv Cryptology"},{"key":"ref31","first-page":"69","article-title":"Pushing the limits: A very compact and a threshold implementation of AES","volume":"6632","author":"moradi","year":"2011","journal-title":"Adv Cryptology"},{"key":"ref30","first-page":"267","article-title":"A more efficient AES threshold implementation","volume":"8469","author":"bilgin","year":"2014","journal-title":"Progress in Cryptology&#x2014;AFRICACRYPT"},{"key":"ref37","first-page":"453","article-title":"Assessment of hiding the higher order leakages in hardware&#x2014;What are the achievements versus overheads?","volume":"9293","author":"moradi","year":"2015","journal-title":"CHES"},{"key":"ref36","first-page":"517","article-title":"Side-channel analysis protection and low-latency in action&#x2014;Case study of PRINCE and Midori","volume":"10031","author":"moradi","year":"2016","journal-title":"Adv Cryptology"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.46586\/tosc.v2017.i1.398-404"},{"key":"ref34","first-page":"33","article-title":"A toolbox for cryptanalysis: Linear and affine equivalence algorithms","volume":"2656","author":"biryukov","year":"2003","journal-title":"Adv Cryptology"},{"key":"ref28","first-page":"326","article-title":"Higher order threshold implementations","volume":"8874","author":"bilgin","year":"2014","journal-title":"Adv Cryptology"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9086-6"},{"key":"ref29","first-page":"79","article-title":"Uniform first-order threshold implementations","volume":"10532","author":"beyne","year":"2017","journal-title":"Proc Selected Areas Cryptography"},{"key":"ref2","first-page":"382","article-title":"Trojan side-channels: Lightweight hardware Trojans through side-channel engineering","volume":"5747","author":"lin","year":"2009","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687425"},{"key":"ref20","first-page":"157","article-title":"Successfully attacking masked AES hardware implementations","volume":"3659","author":"mangard","year":"2005","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref22","first-page":"125","article-title":"Correlation-enhanced power analysis collision attack","volume":"6225","author":"moradi","year":"2010","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref21","first-page":"446","article-title":"A very compact &#x2018;perfectly masked&#x2019; S-box for AES","volume":"5037","author":"canright","year":"2008","journal-title":"Applied Cryptography and Network Security"},{"key":"ref24","first-page":"120","article-title":"Leakage squeezing of order two","volume":"7668","author":"carlet","year":"2012","journal-title":"Progress in Cryptology"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9085-7"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/s12095-014-0104-7"},{"key":"ref25","first-page":"208","article-title":"Leakage squeezing countermeasure against high-order attacks","volume":"6633","author":"maghrebi","year":"2011","journal-title":"Information Security Theory and Practice Security and Privacy of Mobile Devices in Wireless Communication"},{"key":"ref50","year":"2016","journal-title":"Genetic Algorithm"},{"key":"ref51","first-page":"1","article-title":"A testing methodology for side channel resistance validation","author":"goodwill","year":"2011","journal-title":"Proc Non-Invasive Attack Testing Workshop (NIST)"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2339892"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.15"},{"key":"ref52","first-page":"495","article-title":"Leakage assessment methodology&#x2014;A clear roadmap for side-channel evaluations","volume":"9293","author":"schneider","year":"2015","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2018.8383914"},{"key":"ref11","first-page":"450","article-title":"PRESENT: An ultra-lightweight block cipher","volume":"4727","author":"bogdanov","year":"2007","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref40","first-page":"76","article-title":"Threshold implementations of all 3&#x00D7;3 and 4&#x00D7;4 S-boxes","volume":"7428","author":"bilgin","year":"2012","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref12","first-page":"755","article-title":"The first thorough side-channel hardware Trojan","volume":"10624","author":"ender","year":"2017","journal-title":"Adv Cryptology"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2009.5340158"},{"key":"ref14","first-page":"51","article-title":"Hardware Trojan detection using path delay fingerprint","author":"jin","year":"2008","journal-title":"Proc IEEE Int Workshop Hardw -Orient Secur Trust"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2008.61"},{"key":"ref16","first-page":"625","article-title":"A design methodology for stealthy parametric Trojans and its application to bug attacks","volume":"9813","author":"ghandali","year":"2016","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref17","first-page":"221","article-title":"Bug attacks","volume":"5157","author":"biham","year":"2008","journal-title":"Adv Cryptology"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-015-9209-1"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"413","DOI":"10.1007\/11502760_28","article-title":"A side-channel analysis resistant description of the AES S-box","volume":"3557","author":"oswald","year":"2005","journal-title":"Fast Software Encryption"},{"key":"ref4","first-page":"388","article-title":"Differential power analysis","volume":"1666","author":"kocher","year":"1999","journal-title":"Adv Cryptology"},{"key":"ref3","first-page":"104","article-title":"Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems","volume":"1109","author":"kocher","year":"1996","journal-title":"Adv Cryptology"},{"key":"ref6","first-page":"197","article-title":"Stealthy dopant-level hardware Trojans","volume":"8086","author":"becker","year":"2013","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-012-0040-4"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2160375"},{"key":"ref7","first-page":"81","article-title":"Evaluation of the masked logic style MDPL on a prototype chip","volume":"4727","author":"popp","year":"2007","journal-title":"Cryptographic Hardware and Embedded Systems&#x2014;CHES"},{"key":"ref49","first-page":"202","article-title":"Leakage power optimization with dual-Vth library in high-level synthesis","author":"tang","year":"2005","journal-title":"Proc 42nd Ann Conf Des Autom (DAC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2016.10"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857313"},{"key":"ref45","first-page":"342","article-title":"Model for delay faults based upon paths","author":"smith","year":"1985","journal-title":"Proc Int Test Conf"},{"key":"ref48","first-page":"507","article-title":"Low power scheduling in high-level synthesis using dual-Vth library","author":"ghandali","year":"2015","journal-title":"Proc ISQED"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691102"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2419623"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-08302-5_13"},{"key":"ref44","first-page":"131","article-title":"Hiding higher order side-channel leakage&#x2014;Randomizing cryptographic implementations in reconfigurable hardware","volume":"10159","author":"sasdrich","year":"2017","journal-title":"Topics in Cryptology&#x2014;CT-RSA"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2015.14"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/9104037\/9068475-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9104037\/09068475.pdf?arnumber=9068475","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:15Z","timestamp":1651070415000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9068475\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6]]},"references-count":54,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2982473","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,6]]}}}