{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,26]],"date-time":"2026-08-26T15:52:43Z","timestamp":1787759563824,"version":"build-2784847793"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,6,1]],"date-time":"2020-06-01T00:00:00Z","timestamp":1590969600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004541","name":"scholarship from the Ministry of Human Resource and Development, Government of India, through the project Technical Education Quality Improvement Programme-III","doi-asserted-by":"publisher","award":["TEQIP-III"],"award-info":[{"award-number":["TEQIP-III"]}],"id":[{"id":"10.13039\/501100004541","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,6]]},"DOI":"10.1109\/tvlsi.2020.2983850","type":"journal-article","created":{"date-parts":[[2020,4,15]],"date-time":"2020-04-15T22:13:46Z","timestamp":1586988826000},"page":"1413-1422","source":"Crossref","is-referenced-by-count":123,"title":["High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR\u2013XNOR Cell"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4889-5363","authenticated-orcid":false,"given":"Jyoti","family":"Kandpal","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Abhishek","family":"Tomar","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0729-4606","authenticated-orcid":false,"given":"Mayur","family":"Agarwal","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"K. K.","family":"Sharma","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"5","article-title":"A novel hybrid pass logic with static CMOS output drive full-adder cell","volume":"5","author":"zhang","year":"2003","journal-title":"Proc Int Symp Circuits Syst (ISCAS)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.0893"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2357057"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20010170"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527335"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2820999"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/82.996055"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.01.018"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2011.6122310"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.848806"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.887807"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2038166"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.133177"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SPIN.2014.6776995"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2013.05.001"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.597298"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.1999.822379"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9104037\/09068497.pdf?arnumber=9068497","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:14Z","timestamp":1651070414000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9068497\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,6]]},"references-count":18,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2983850","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,6]]}}}