{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:24:25Z","timestamp":1772119465587,"version":"3.50.1"},"reference-count":54,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,7,1]],"date-time":"2020-07-01T00:00:00Z","timestamp":1593561600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Center for Brain-inspired Computing Enabling Autonomous Intelligence"},{"name":"one of the six centers in the Joint University Microelectronics Program"},{"DOI":"10.13039\/100000028","name":"a Semiconductor Research Corporation (SRC) Program","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000185","name":"Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,7]]},"DOI":"10.1109\/tvlsi.2020.2993045","type":"journal-article","created":{"date-parts":[[2020,5,20]],"date-time":"2020-05-20T20:43:13Z","timestamp":1590007393000},"page":"1567-1577","source":"Crossref","is-referenced-by-count":40,"title":["TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2291-7712","authenticated-orcid":false,"given":"Shubham","family":"Jain","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5609-9722","authenticated-orcid":false,"given":"Sumeet Kumar","family":"Gupta","sequence":"additional","affiliation":[]},{"given":"Anand","family":"Raghunathan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662419"},{"key":"ref38","first-page":"52","article-title":"A \n$2\\times30$\n k-spin multichip scalable annealing processor based on a processing-in-memory approach for solving large-scale combinatorial optimization problems","author":"takemoto","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref33","first-page":"246","article-title":"A 28 nm 64 Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips","author":"si","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref32","first-page":"500","article-title":"A fully integrated analog ReRAM based 78.4 TOPS\/W compute-in-memory chip with fully parallel MAC computing","author":"liu","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"ref30","article-title":"Xcel-RAM: Accelerating binary neural networks in high-throughput SRAM compute arrays","volume":"abs 1807 343","author":"agrawal","year":"2018","journal-title":"CoRR"},{"key":"ref37","first-page":"234","article-title":"A 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS\/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter\/intra-macro data reuse","author":"yue","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref36","first-page":"240","article-title":"A 28 nm 64 Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips","author":"su","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref35","first-page":"242","article-title":"A 351 TOPS\/W and 372.4 GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","author":"dong","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","first-page":"244","article-title":"A 22 nm 2 Mb ReRAM compute-in-memory macro with 121-28 TOPS\/W for multibit MAC computing for tiny AI edge devices","author":"xue","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","first-page":"21:1","article-title":"Parallelizing SRAM arrays with customized bit-cell for binary neural networks","author":"liu","year":"2018","journal-title":"Proc 55th Annu Design Autom Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310397"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2016.7428029"},{"key":"ref1","author":"metz","year":"2017","journal-title":"Google Facebook and Microsoft are remaking themselves around AI"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342235"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744900"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297384"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627625"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304049"},{"key":"ref50","article-title":"8T SRAM cell as a multibit dot-product engine for beyond Von Neumann computing","volume":"abs 1802 8601","author":"jaiswal","year":"2018","journal-title":"CoRR"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178127"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2121913"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref10","article-title":"Ternary neural networks for resource-efficient AI applications","volume":"abs 1609 222","author":"alemdar","year":"2016","journal-title":"CoRR"},{"key":"ref11","first-page":"604","article-title":"HitNet: Hybrid ternary recurrent neural network","author":"wang","year":"2018","journal-title":"Advances in Neural IInformation Processing Systems"},{"key":"ref40","first-page":"396","article-title":"A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning","author":"si","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","article-title":"Ternary neural networks with fine-grained quantization","volume":"abs 1705 1462","author":"mellempudi","year":"2017","journal-title":"CoRR"},{"key":"ref13","article-title":"Effective quantization methods for recurrent neural networks","volume":"abs 1611 10176","author":"he","year":"2016","journal-title":"CoRR"},{"key":"ref14","article-title":"PACT: Parameterized clipping activation for quantized neural networks","volume":"abs 1805 6085","author":"choi","year":"2018","journal-title":"CoRR"},{"key":"ref15","year":"2019"},{"key":"ref16","year":"2019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3195970.3196012"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref19","first-page":"5","author":"taylor","year":"2003","journal-title":"The Penn treebank an overview"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627613"},{"key":"ref6","article-title":"DoReFa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","volume":"abs 1606 6160","author":"zhou","year":"2016","journal-title":"CoRR"},{"key":"ref5","article-title":"BinaryConnect: Training deep neural networks with binary weights during propagations","volume":"abs 1511 363","author":"courbariaux","year":"2015","journal-title":"CoRR"},{"key":"ref8","article-title":"Trained ternary quantization","volume":"abs 1612 1064","author":"zhu","year":"2016","journal-title":"CoRR"},{"key":"ref7","article-title":"Neural networks with few multiplications","volume":"abs 1510 3009","author":"lin","year":"2015","journal-title":"CoRR"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00040"},{"key":"ref9","article-title":"WRPN: Wide reduced-precision networks","volume":"abs 1709 1134","author":"asit mishra","year":"2017","journal-title":"CoRR"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.3850\/9783981537079_0549"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008533"},{"key":"ref47","article-title":"RxNN: A framework for evaluating deep neural networks on resistive crossbars","volume":"abs 1809 72","author":"jain","year":"2018","journal-title":"CoRR"},{"key":"ref42","first-page":"494","article-title":"A 65 nm 1 Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors","author":"chen","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref41","first-page":"496","article-title":"A 65 nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref44","first-page":"490","article-title":"A 42 pJ\/decision 3.12 TOPS\/W robust in-memory machine learning classifier with on-chip training","author":"gonugondla","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310399"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9127213\/09097464.pdf?arnumber=9097464","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:04Z","timestamp":1651070404000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9097464\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7]]},"references-count":54,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2993045","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,7]]}}}