{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:26Z","timestamp":1740133286205,"version":"3.37.3"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,8]]},"DOI":"10.1109\/tvlsi.2020.2996544","type":"journal-article","created":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T22:36:16Z","timestamp":1592260576000},"page":"1782-1795","source":"Crossref","is-referenced-by-count":6,"title":["PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6789-3710","authenticated-orcid":false,"given":"Mahdi","family":"Yektaei","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7026-9476","authenticated-orcid":false,"given":"M. B.","family":"Ghaznavi-Ghoushchi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875092"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948891"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1016\/j.mejo.2017.07.009","article-title":"MTCML: Analysis, design and optimization of an alternative shallow-depth multiple-tail current mode logic","volume":"67","author":"b","year":"2017","journal-title":"Microelectron J"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/92.748196"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.2002.1158055"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2004.1362338"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2006.03.009"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2239161"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/82.700924"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.1995.535518"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2919186"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2006.264841"},{"key":"ref27","first-page":"233","article-title":"A novel 0.6 V MCML D-latch topology exploiting dynamic body bias threshold lowering","author":"scotti","year":"2018","journal-title":"Proc IEEE Int Conf Electronics Circuits Syst (ICECS)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.833663"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.801195"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922709"},{"key":"ref8","first-page":"1","article-title":"Design and physical implementation of an analog receiver for a SerDes system on chip in 130 nm CMOS technology","author":"almada","year":"2016","journal-title":"IEEE MTT-S Int Microw Symp Dig"},{"key":"ref7","first-page":"13","article-title":"A 12.5 Gbps transmitter for multi-standard SERDES in 40 nm low leakage CMOS process","author":"chattopadhyay","year":"2018","journal-title":"Proc 31st Int Conf VLSI Design 17th Int Conf Embedded Syst (VLSID)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-91307-0_7"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2017.8368879"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310210"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008275"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/4.848210"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780831"},{"key":"ref23","first-page":"309","article-title":"Ultra-low power 50\/60 Hz notch filter for biomedical signal acquisition using 32nm &#x00B1;0.15 V bulk-driven subthreshold CMOS OTAs","author":"ansari","year":"2017","journal-title":"Proc 4th Int Conf Electr Electron Eng (ICEEE)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2003.1213986"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541453"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9151408\/09116821.pdf?arnumber=9116821","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:26Z","timestamp":1651070426000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9116821\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8]]},"references-count":28,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.2996544","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,8]]}}}