{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:26Z","timestamp":1740133286193,"version":"3.37.3"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/tvlsi.2020.3003091","type":"journal-article","created":{"date-parts":[[2020,7,2]],"date-time":"2020-07-02T20:36:18Z","timestamp":1593722178000},"page":"2042-2054","source":"Crossref","is-referenced-by-count":2,"title":["An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7434-8075","authenticated-orcid":false,"given":"Qian","family":"Ding","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8255-1225","authenticated-orcid":false,"given":"Graham","family":"Knight","sequence":"additional","affiliation":[]},{"given":"Terrence","family":"Mak","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"The Mali-G77 Graphics Processors","year":"2019","key":"ref31"},{"key":"ref30","first-page":"83","article-title":"Scalable, sub-1W, sub-10ps clock skew, global clock distribution architecture for Intel Core i7\/i5\/i3 microprocessors","author":"shamanna","year":"2010","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.905235"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351041"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/el.2018.6570"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.664231"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560197"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243962"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2012.2226746"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/5.920578"},{"journal-title":"Design of Analog CMOS Integrated Circuits","year":"2001","author":"razavi","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.850409"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.44.2756"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/196244.196430"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2003.1219740"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106806"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830808"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.962284"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2012.2204392"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2015.2510199"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818951"},{"journal-title":"Predictive Technology Model (PTM)","year":"2012","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.997846"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2012","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2008.4483951"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.841065"},{"key":"ref21","first-page":"478","article-title":"Modeling and optimization of low power resonant clock mesh","author":"liu","year":"2015","journal-title":"Proc Asia South Pacific Design Automat Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034806"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CSAE.2012.6272582"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LAWP.2012.2184255"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"279","DOI":"10.1109\/LAWP.2008.928472","article-title":"Meander-line folded monopole design for UMTS-HSDAP-based data-card applications","volume":"7","author":"hu","year":"2008","journal-title":"IEEE Antennas Wireless Propag Lett"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9177384\/09132717.pdf?arnumber=9132717","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:18Z","timestamp":1651070418000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9132717\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":31,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3003091","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}