{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:45:00Z","timestamp":1761324300211,"version":"3.37.3"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,9,1]],"date-time":"2020-09-01T00:00:00Z","timestamp":1598918400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100008530","name":"Ministerio de Econom\u00eda y Empresa (MINECO)\/Agencia Estatal de Investigaci\u00f3n (AEI)\/European Regional Development Fund (ERDF)","doi-asserted-by":"publisher","award":["TIN2016-76635-C2-1-R","TIN2017-87237-9","PID2019-105660RB-C21"],"award-info":[{"award-number":["TIN2016-76635-C2-1-R","TIN2017-87237-9","PID2019-105660RB-C21"]}],"id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100010067","name":"Arag\u00f3n Government Research Group","doi-asserted-by":"publisher","award":["ERDF 2014-2020"],"award-info":[{"award-number":["ERDF 2014-2020"]}],"id":[{"id":"10.13039\/501100010067","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,9]]},"DOI":"10.1109\/tvlsi.2020.3005451","type":"journal-article","created":{"date-parts":[[2020,7,8]],"date-time":"2020-07-08T20:26:22Z","timestamp":1594239982000},"page":"1993-2003","source":"Crossref","is-referenced-by-count":12,"title":["Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7057-4283","authenticated-orcid":false,"given":"Adrian Alcolea","family":"Moreno","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7752-8714","authenticated-orcid":false,"given":"Javier","family":"Olivito","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7532-2720","authenticated-orcid":false,"given":"Javier","family":"Resano","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9774-4609","authenticated-orcid":false,"given":"Hortensia","family":"Mecha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"WT210\/WT230 Digital Power Meters","year":"2020","key":"ref33"},{"journal-title":"Zynq Ultrascale+ MPSoC ZCU104 Evaluation Kit SoC and FPGA Platform","year":"2020","key":"ref32"},{"article-title":"Automatic performance tuning of sparse matrix kernels","year":"0","author":"vuduc","key":"ref31"},{"journal-title":"Pipelined Architecture for Sparse DNNs","year":"2018","author":"alcolea","key":"ref30"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"journal-title":"Squeezenet Deep Compression&#x2014;GitHub Repository","year":"2016","author":"han","key":"ref10"},{"journal-title":"Deep Compression AlexNet&#x2014;Github Repository","year":"2016","author":"han","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/s00521-018-3761-1"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3186332"},{"key":"ref14","first-page":"598","article-title":"Optimal brain damage","author":"lecun","year":"1990","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref15","first-page":"164","article-title":"Second order derivatives for network pruning: Optimal brain surgeon","author":"hassibi","year":"1993","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref16","first-page":"1135","article-title":"Learning both weights and connections for efficient neural network","author":"han","year":"2015","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.643"},{"key":"ref18","article-title":"To prune, or not to prune: Exploring the efficacy of pruning for model compression","author":"zhu","year":"2017","journal-title":"arXiv 1710 01878"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080215"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref4","first-page":"1","article-title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and Huffman coding","author":"han","year":"2016","journal-title":"Proc Int Conf Learn Represent"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080254"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref6","article-title":"Incremental network quantization: Towards lossless CNNs with low-precision weights","author":"zhou","year":"2017","journal-title":"arXiv 1702 03044"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref5","article-title":"Trained ternary quantization","author":"zhu","year":"2016","journal-title":"arXiv 1612 01064"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig48160.2019.8994751"},{"key":"ref7","article-title":"NESTA: Hamming weight compression-based neural Proc. Engine","author":"mirzaeian","year":"2019","journal-title":"arXiv 1910 00700"},{"key":"ref2","article-title":"ADaPTION: Toolbox and benchmark for training convolutional neural networks with reduced numerical precision weights and activation","author":"milde","year":"2017","journal-title":"arXiv 1711 04713"},{"key":"ref9","article-title":"SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and < 0.5MB model size","author":"iandola","year":"2016","journal-title":"arXiv 1602 07360"},{"key":"ref1","article-title":"Hardware-oriented approximation of convolutional neural networks","author":"gysel","year":"2016","journal-title":"arXiv 1604 03168"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293898"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001163"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001138"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2924215"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00062"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2018.2852335"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783723"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9177384\/09136784.pdf?arnumber=9136784","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:18Z","timestamp":1651070418000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9136784\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,9]]},"references-count":34,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3005451","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,9]]}}}