{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:27Z","timestamp":1740133287015,"version":"3.37.3"},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,10,1]],"date-time":"2020-10-01T00:00:00Z","timestamp":1601510400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2020,10]]},"DOI":"10.1109\/tvlsi.2020.3013139","type":"journal-article","created":{"date-parts":[[2020,8,14]],"date-time":"2020-08-14T20:33:42Z","timestamp":1597437222000},"page":"2223-2227","source":"Crossref","is-referenced-by-count":0,"title":["Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping"],"prefix":"10.1109","volume":"28","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3333-1071","authenticated-orcid":false,"given":"Even","family":"Late","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2109-833X","authenticated-orcid":false,"given":"Trond","family":"Ytterdal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6465-8886","authenticated-orcid":false,"given":"Snorre","family":"Aunet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.2540"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2160812"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.816139"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2015.0318"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000249"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831471"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2016.7598333"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/92.365453"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9206095\/09167447.pdf?arnumber=9167447","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T14:40:15Z","timestamp":1651070415000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9167447\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,10]]},"references-count":8,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3013139","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2020,10]]}}}