{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:29Z","timestamp":1740133289028,"version":"3.37.3"},"reference-count":59,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"German Federal Ministry of Education and Research","doi-asserted-by":"publisher","award":["16KIS0610"],"award-info":[{"award-number":["16KIS0610"]}],"id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tvlsi.2020.3023548","type":"journal-article","created":{"date-parts":[[2020,9,23]],"date-time":"2020-09-23T20:44:09Z","timestamp":1600893849000},"page":"38-50","source":"Crossref","is-referenced-by-count":3,"title":["Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3698-8658","authenticated-orcid":false,"given":"Nadir","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4808-4904","authenticated-orcid":false,"given":"Jorge","family":"Castro-Godinez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shixiang","family":"Xue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9602-2922","authenticated-orcid":false,"given":"Jorg","family":"Henkel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5082-5487","authenticated-orcid":false,"given":"Jurgen","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4630038"},{"journal-title":"Gurobi Optimization Documentation","year":"2020","key":"ref38"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.104"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470756"},{"key":"ref31","first-page":"6","article-title":"Heterogeneous floorplanning for FPGAs","author":"feng","year":"2006","journal-title":"Proc 19th Int Conf VLSI Des Held Jointly"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689085"},{"journal-title":"Partial ReconfigurationUser Guide","year":"2013","key":"ref37"},{"journal-title":"Gurobi Optimizer","year":"2020","key":"ref36"},{"journal-title":"Milp-Formulation","year":"2020","author":"khan","key":"ref35"},{"key":"ref34","first-page":"13","article-title":"Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration","author":"vipin","year":"2012","journal-title":"Proc 8th Int Conf Reconfigurable Comput"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2010.5681429"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2018.00030"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2011.69"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339165"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344729"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2169667"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2437996"},{"key":"ref21","first-page":"169","article-title":"Dynamic intellectual property protection for reconfigurable devices","author":"g\u00e1neysu","year":"2008","journal-title":"Proc Int Conf Field-Program Technol"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629918"},{"key":"ref23","first-page":"37","article-title":"GoAhead: A partial reconfiguration framework","author":"beckhoff","year":"2012","journal-title":"Proc 20th Int Symp Field-Program Custom Comput Mach"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056809"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.146"},{"journal-title":"The Transport Layer Security (TLS) Protocol Version 1 3","year":"2020","key":"ref50"},{"journal-title":"Developing Tamper-Resistant Designs with UltraScale UltraScale+ FPGAs","year":"2018","key":"ref51"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822126"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/43.952741"},{"key":"ref57","first-page":"118","article-title":"A chaotic ip watermarking in physical layout level based on FPGA","volume":"20","author":"liang","year":"2011","journal-title":"Radioengineering"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-007-0136-8"},{"key":"ref55","first-page":"286","article-title":"Checking for electrical level security threats in bitstreams for multi-tenant FPGAs","author":"gnad","year":"2018","journal-title":"Proc IEEE Int Conf Field-Programmable Technol (FPT)"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.7"},{"journal-title":"Ultra Scale Architecture Configuration User Guide","year":"2018","key":"ref53"},{"key":"ref52","first-page":"33","article-title":"Generic side-channel countermeasures for reconfigurable devices","volume":"6917","author":"g\u00fcneysu","year":"2011","journal-title":"Cryptographic Hardware and Embedded Systems—CHES"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168561"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"137","DOI":"10.1007\/978-3-030-17227-5_11","article-title":"Secure local configuration of intellectual property without a trusted third party","author":"khan","year":"2019","journal-title":"Applied Reconfigurable Computing"},{"journal-title":"Opencores LZRW1 Compressor Core","year":"2020","author":"schrittwieser","key":"ref40"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.5220\/0007576305640571"},{"journal-title":"Vivado design suite user guide Partial reconfiguration (ug909)","year":"2019","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2014.61"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2562361"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/RECONFIG.2018.8641731"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3358202"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/503062.503065"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2015.2400413"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.24"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2755563"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2016.7800555"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3340557"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2355043"},{"key":"ref7","first-page":"53","article-title":"Amplifying side channel leakage by hardware modification of xilinx Zynq-7 FPGA evaluation boards","author":"khan","year":"2019","journal-title":"Proc 13th Int Conf Emerg Secur Inf Syst Technol"},{"journal-title":"Vivado Design Suite User Guide Hierarchical Design UG905","year":"2018","key":"ref49"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-014-0088-4"},{"journal-title":"Opencores Pipelined DCT\/IDCT","year":"2020","author":"uzenkov","key":"ref46"},{"journal-title":"Opencores Discrete Cosine Transform Core","year":"2020","author":"krepa","key":"ref45"},{"journal-title":"AXI Reference Guide","year":"2011","key":"ref48"},{"journal-title":"Opencores Sha-256 Core","year":"2020","author":"de la piedra","key":"ref47"},{"journal-title":"Opencores Xtea Core","year":"2020","author":"de la piedra","key":"ref42"},{"journal-title":"Opencores Universal Multi-Function Cordic","year":"2020","author":"kavvadias","key":"ref41"},{"journal-title":"Opencore Canny Edge Detectore","year":"2020","key":"ref44"},{"journal-title":"Opencores B-163 EC Arithmetic","year":"2020","author":"bacchini","key":"ref43"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9311741\/09204756.pdf?arnumber=9204756","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:22Z","timestamp":1652194222000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9204756\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":59,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3023548","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}