{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,7]],"date-time":"2025-08-07T09:11:33Z","timestamp":1754557893156,"version":"3.37.3"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,1,1]],"date-time":"2021-01-01T00:00:00Z","timestamp":1609459200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,1]]},"DOI":"10.1109\/tvlsi.2020.3029729","type":"journal-article","created":{"date-parts":[[2020,10,22]],"date-time":"2020-10-22T19:48:17Z","timestamp":1603396097000},"page":"89-99","source":"Crossref","is-referenced-by-count":2,"title":["Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5491-7282","authenticated-orcid":false,"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2018.8624752"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2005.53"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2022474"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966682"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741614"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437648"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776000"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.40"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116296"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556969"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"1128","DOI":"10.1109\/43.406714","article-title":"Test application time reduction for sequential circuits with scan","volume":"14","author":"young lee","year":"1995","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2017.0239"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9311741\/09237170.pdf?arnumber=9237170","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:22Z","timestamp":1652194222000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9237170\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1]]},"references-count":13,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3029729","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2021,1]]}}}