{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T19:50:24Z","timestamp":1771703424252,"version":"3.50.1"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,3,1]],"date-time":"2021-03-01T00:00:00Z","timestamp":1614556800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100010663","name":"European Union European Research Council (EU ERC) project ReSENSE","doi-asserted-by":"publisher","award":["ERC-2016-STG-715037"],"award-info":[{"award-number":["ERC-2016-STG-715037"]}],"id":[{"id":"10.13039\/100010663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003130","name":"Fonds Wetenschappelijk Onderzoek Strategisch Basis Onderzoek (FWO SBO) project OmniDrone","doi-asserted-by":"publisher","award":["S003817N"],"award-info":[{"award-number":["S003817N"]}],"id":[{"id":"10.13039\/501100003130","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Flemish Government through the AI Research Program"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,3]]},"DOI":"10.1109\/tvlsi.2020.3046125","type":"journal-article","created":{"date-parts":[[2021,1,14]],"date-time":"2021-01-14T22:18:54Z","timestamp":1610662734000},"page":"461-471","source":"Crossref","is-referenced-by-count":30,"title":["High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4199-2926","authenticated-orcid":false,"given":"Steven","family":"Colleman","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3495-9263","authenticated-orcid":false,"given":"Marian","family":"Verhelst","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2014","journal-title":"arXiv 1409 1556"},{"key":"ref11","article-title":"YOLOv3: An incremental improvement","author":"redmon","year":"2018","journal-title":"arXiv 1804 02767"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW50202.2020.00032"},{"key":"ref13","author":"annadurai","year":"2007","journal-title":"Fundamentals of Digital Image Processing"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929545"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1587\/transfun.E101.A.2280"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCI.2016.2644865"},{"key":"ref17","first-page":"2287","article-title":"Stereo matching by training a convolutional neural network to compare image patches","volume":"17","author":"\u017ebontar","year":"2016","journal-title":"J Mach Learn Res"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2017.291"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783725"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2018.2818644"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HUMANOIDS.2017.8246891"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021736"},{"key":"ref8","first-page":"61","article-title":"Automatic code generation of convolutional neural networks in FPGA implementation","author":"liu","year":"2016","journal-title":"Proc Int Conf Field-Program Technol (FPT)"},{"key":"ref7","first-page":"1","article-title":"A high performance FPGA-based accelerator for large-scale convolutional neural networks","author":"li","year":"2016","journal-title":"Proc Int Conf Field Program Logic Appl (FPL)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351244"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2881162"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3065386"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2905361"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378514"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062244"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref23","author":"sewak","year":"2018","journal-title":"Practical Convolutional Neural Networks Implement Advanced Deep Learning Models Using Python"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9361476\/09324820.pdf?arnumber=9324820","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:22Z","timestamp":1652194222000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9324820\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,3]]},"references-count":24,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2020.3046125","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,3]]}}}