{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:32Z","timestamp":1740133292707,"version":"3.37.3"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1640020"],"award-info":[{"award-number":["1640020"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Nanoelectronics Research Corporation"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation (SRC) through an SRC-NRI Nanoelectronics Research Initiative","doi-asserted-by":"publisher","award":["2699.004"],"award-info":[{"award-number":["2699.004"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/tvlsi.2021.3059979","type":"journal-article","created":{"date-parts":[[2021,3,9]],"date-time":"2021-03-09T21:40:51Z","timestamp":1615326051000},"page":"691-701","source":"Crossref","is-referenced-by-count":0,"title":["Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5524-1050","authenticated-orcid":false,"given":"Saambhavi","family":"Baskaran","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jack","family":"Sampson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"227","article-title":"Pathfinding for 22 nm CMOS designs using predictive technology models","author":"li","year":"2009","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"year":"2011","journal-title":"Predictive Technology Model","key":"ref38"},{"doi-asserted-by":"publisher","key":"ref33","DOI":"10.1063\/1.4869142"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"26663","DOI":"10.1038\/srep26663","article-title":"Pressure coefficients for direct optical transitions in MoS?, MoSe?, WS?, and WSe? crystals and semiconductor to metal transitions","volume":"6","author":"dyba?a","year":"2016","journal-title":"Sci Rep"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1063\/1.4971404"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/TED.2020.2999317"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1145\/2897937.2897984"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/MICRO.2003.1253179"},{"year":"2018","author":"thakuria","article-title":"2D electrostrictive FET based circuits: Compact modeling and device-circuit co-design","key":"ref35"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1063\/1.4882025"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1038\/srep34811"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.1109\/ISVLSI.2017.31"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/VLSI-TSA.2018.8403841"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/DRC.2018.8442149"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TVLSI.2010.2063444"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TVLSI.2013.2259512"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/FPL.2012.6339206"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/ISSCC.2012.6177067"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/FPT.2014.7082777"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/FPT.2012.6412139"},{"year":"2019","author":"schulman","article-title":"Contact, interface, and strain engineering of two-dimensional transition metal dichalcogenide field effect transistors","key":"ref19"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1038\/ncomms4731"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/JPROC.2013.2252317"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1088\/0965-0393\/21\/6\/065015"},{"key":"ref3","first-page":"365","article-title":"Dark silicon and the end of multicore scaling","author":"esmaeilzadeh","year":"2011","journal-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA) ISCA"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1038\/nature10679"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/TED.2020.3022344"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/JXCDC.2015.2418033"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1038\/nnano.2010.279"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TED.2016.2514783"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1145\/1736020.1736044"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TVLSI.2019.2914609"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JSSC.1974.1050511"},{"key":"ref20","first-page":"5.6.1","article-title":"Approaching ballistic transport in monolayer MoS? transistors with self-aligned 10 nm top gates","author":"english","year":"2016","journal-title":"IEDM Tech Dig"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1109\/CICC.1999.777267"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1038\/ncomms14948"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1038\/nature14417"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1145\/2617593"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.23919\/DATE.2018.8342088"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/LASCAS.2015.7250433"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1021\/nl302015v"},{"doi-asserted-by":"publisher","key":"ref44","DOI":"10.1145\/2145694.2145708"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1038\/ncomms5214"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.1007\/978-1-4615-5145-4"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1103\/PhysRevB.87.235434"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/9390228\/9373693-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9390228\/09373693.pdf?arnumber=9373693","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:33Z","timestamp":1652194233000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9373693\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":45,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3059979","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}