{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T10:26:41Z","timestamp":1771064801858,"version":"3.50.1"},"reference-count":61,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,4,1]],"date-time":"2021-04-01T00:00:00Z","timestamp":1617235200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,4]]},"DOI":"10.1109\/tvlsi.2021.3060345","type":"journal-article","created":{"date-parts":[[2021,3,4]],"date-time":"2021-03-04T20:51:37Z","timestamp":1614891097000},"page":"643-656","source":"Crossref","is-referenced-by-count":19,"title":["Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits"],"prefix":"10.1109","volume":"29","author":[{"given":"Kimia","family":"Zamiri Azar","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4246-6736","authenticated-orcid":false,"given":"Hadi Mardani","family":"Kamali","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3407-449X","authenticated-orcid":false,"given":"Shervin","family":"Roshanisefat","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8904-4699","authenticated-orcid":false,"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9318-474X","authenticated-orcid":false,"given":"Christos P.","family":"Sotiriou","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4052-8075","authenticated-orcid":false,"given":"Avesta","family":"Sasan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968552"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-66787-4_10"},{"key":"ref33","article-title":"Encrypt flip-flop: A novel logic encryption technique for sequential circuits","author":"karmakar","year":"2018","journal-title":"arXiv 1801 04961"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317831"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194580"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062226"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3029133"},{"key":"ref36","article-title":"Efficient key-gate placement and dynamic scan obfuscation towards robust logic encryption","author":"karmakar","year":"2019","journal-title":"IEEE Trans Emerg Topics Comput"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2797019"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2893183"},{"key":"ref60","article-title":"Latch-based logic locking","author":"sweeney","year":"2020","journal-title":"arXiv 2005 10649"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.358004"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194596"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3060403.3060458"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8341984"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"ref1","article-title":"Trends in the global IC design service market","author":"yeh","year":"2012","journal-title":"Proc DIGITIMES"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942047"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287693"},{"key":"ref21","first-page":"1","article-title":"On designing secure and robust scan chain for protecting obfuscated logic","author":"kamali","year":"2020","journal-title":"Proc Great Lakes Symp (VLSI)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2016.7495588"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116197"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3133956.3133985"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-53140-2_7"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927276"},{"key":"ref51","first-page":"315","article-title":"A tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"80","author":"cortadella","year":"1997","journal-title":"IEICE"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00036"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00022"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2018.00021"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(95)00012-5"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/92.502196"},{"key":"ref54","article-title":"Register retiming technique","author":"van antwerpen","year":"2006"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.860958"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/5.24143"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2017.2740364"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951805"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3287670"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2020.2968183"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203759"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942049"},{"key":"ref15","first-page":"97","article-title":"SMT attack: Next generation attack on obfuscated circuits with capabilities and performance beyond the SAT attacks","volume":"1","author":"azar","year":"2019","journal-title":"Proc IACR Trans Cryptograph Hardw Embedded Syst"},{"key":"ref16","first-page":"1","article-title":"InterLock: An intercorrelated logic and routing locking","author":"kamali","year":"2020","journal-title":"Proc 39th Int Conf Computer-Aided Design"},{"key":"ref17","first-page":"1","article-title":"NNgSAT: Neural network guided SAT attack on logic locked complex structures","author":"azar","year":"2020","journal-title":"Proc 39th Int Conf Comput -Aided Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203757"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8715053"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1403375.1403631"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2017.7906898"},{"key":"ref6","first-page":"471","article-title":"Threats on logic locking: A decade later","author":"azar","year":"2019","journal-title":"Proc Great Lakes Symp (VLSI)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228377"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140252"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3342099"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2573864"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2755563"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00017"},{"key":"ref45","first-page":"49","article-title":"Logic synthesis for asynchronous circuits based on STG unfoldings and SAT","volume":"70","author":"khomenko","year":"2006","journal-title":"Fundamenta Informaticae"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00016"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2019.00009"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00068"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2772817"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2015.2413759"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516656"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/9390228\/9369866-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9390228\/09369866.pdf?arnumber=9369866","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:33Z","timestamp":1652194233000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9369866\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,4]]},"references-count":61,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3060345","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,4]]}}}