{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:09:10Z","timestamp":1773248950938,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,5,1]],"date-time":"2021-05-01T00:00:00Z","timestamp":1619827200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,5]]},"DOI":"10.1109\/tvlsi.2021.3061484","type":"journal-article","created":{"date-parts":[[2021,3,22]],"date-time":"2021-03-22T20:34:20Z","timestamp":1616445260000},"page":"962-972","source":"Crossref","is-referenced-by-count":24,"title":["Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8616-2366","authenticated-orcid":false,"given":"Dimitrios","family":"Garyfallou","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0015-7510","authenticated-orcid":false,"given":"Stavros","family":"Simoglou","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6501-4209","authenticated-orcid":false,"given":"Nikolaos","family":"Sketopoulos","sequence":"additional","affiliation":[]},{"given":"Charalampos","family":"Antoniadis","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9318-474X","authenticated-orcid":false,"given":"Christos P.","family":"Sotiriou","sequence":"additional","affiliation":[]},{"given":"Nestor","family":"Evmorfopoulos","sequence":"additional","affiliation":[]},{"given":"George","family":"Stamoulis","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/43.331409"},{"key":"ref11","first-page":"826","article-title":"Library compatible ceff for gate-level timing","author":"sheehan","year":"2002","journal-title":"Proc DATE Conf Exhib"},{"key":"ref12","first-page":"866","article-title":"Osculating Thevenin model for predicting delay and slew of capacitively characterized cells","author":"sheehan","year":"2002","journal-title":"Proc 39th Annu DAC"},{"key":"ref13","first-page":"43","article-title":"Calculating the effective capacitance for the RC interconnect in VDSM technologies","author":"abbaspour","year":"2003","journal-title":"Proc ASP-DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/43.506141"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1999.745217"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2007.4299530"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.862739"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391580"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/505306.505314"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775933"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776030"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176629"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391589"},{"key":"ref8","year":"2020","journal-title":"Cadence&#x2014;Effective Current Source Model (ECSM)"},{"key":"ref7","year":"2020","journal-title":"Synopsys&#x2014;Composite Current Source (CCS)"},{"key":"ref2","author":"bhasker","year":"2009","journal-title":"Static Timing Analysis for Nanometer Designs A Practical Approach"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1989.77002"},{"key":"ref1","year":"2020","journal-title":"Synopsys&#x2014;HSPICE"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/S0377-0427(00)00396-4"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED48828.2020.9137017"},{"key":"ref21","first-page":"468","article-title":"Challenges in gate level modeling for delay and SI at 65 nm and below","author":"keller","year":"2008","journal-title":"Proc 45th Annu DAC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref23","year":"2020","journal-title":"TAU 2020 Timing Contest&#x2014;Delay Calculator Using Current Source Models"},{"key":"ref25","year":"2020","journal-title":"ASU&#x2014;ASAP7 PDK"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9416715\/09382263.pdf?arnumber=9382263","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:23Z","timestamp":1652194223000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9382263\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,5]]},"references-count":25,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3061484","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,5]]}}}