{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T11:59:16Z","timestamp":1792756756593,"version":"4.5.0"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,6]]},"DOI":"10.1109\/tvlsi.2021.3065639","type":"journal-article","created":{"date-parts":[[2021,3,30]],"date-time":"2021-03-30T20:45:35Z","timestamp":1617137135000},"page":"1178-1191","source":"Crossref","is-referenced-by-count":56,"title":["Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9865-8390","authenticated-orcid":false,"given":"Chung-Kuan","family":"Cheng","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6479-7552","authenticated-orcid":false,"given":"Chia-Tung","family":"Ho","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0778-0110","authenticated-orcid":false,"given":"Daeyeal","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0965-7247","authenticated-orcid":false,"given":"Bill","family":"Lin","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1508-3315","authenticated-orcid":false,"given":"Dongwon","family":"Park","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993635"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/EDTM.2019.8731234"},{"key":"ref30","article-title":"DTCO exploration for efficient standard cell power rails","volume":"10588","author":"chava","year":"2018","journal-title":"Proc SPIE Des -Process-Technol Co-Optim Manufacturability"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2910579"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC47756.2020.9045729"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-46681-0_14"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2742060.2742084"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062302"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2842612"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3299902.3309744"},{"key":"ref17","first-page":"1","article-title":"Standard-cell scaling framework with guaranteed pin-accessibility","author":"cheng","year":"2020","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2977066"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3299902.3309752"},{"key":"ref28","year":"2020","journal-title":"LEF\/DEF Language Reference"},{"key":"ref4","article-title":"Design technology co-optimization approaches for integration and migration to CFET and 3D logic","author":"smith","year":"2019","journal-title":"Proc Surf Preparation Cleaning Conf (SPCC)"},{"key":"ref27","year":"2020","journal-title":"Cadence Innovus User Guide"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1117\/12.2299335"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/266021.266126"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2018.8430415"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.2514571"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3036669.3036672"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.79"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1117\/12.2554025"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317868"},{"key":"ref1","first-page":"1","article-title":"Design technology co-optimization for 3 nm and beyond","author":"liebmann","year":"2019","journal-title":"IEDM Tech Dig"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1117\/12.917775"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3225209.3225210"},{"key":"ref24","first-page":"1","article-title":"A routability-driven complimentary-FET (CFET) standard cell synthesis framework using SMT","author":"cheng","year":"2020","journal-title":"Proc 39th Int Conf Computer-Aided Design"},{"key":"ref23","article-title":"Standard-cell design architecture options below 5 nm node: The ultimate scaling of finfet and nanosheet","volume":"10962","author":"sherazi","year":"2019","journal-title":"Proc SPIE Int Soc Opt Photon"},{"key":"ref26","year":"2020","journal-title":"OpenCores Open Source IP-Cores"},{"key":"ref25","first-page":"1","article-title":"Design flows and collateral for the ASAP7 7 nm FinFET predictive process design kit","author":"clark","year":"2017","journal-title":"Proc IEEE Int Conf Microelectron Syst Educ (MSE)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9445837\/09390403.pdf?arnumber=9390403","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:34Z","timestamp":1652194234000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9390403\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6]]},"references-count":32,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3065639","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6]]}}}