{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,11]],"date-time":"2026-02-11T18:12:46Z","timestamp":1770833566542,"version":"3.50.1"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,8,1]],"date-time":"2021-08-01T00:00:00Z","timestamp":1627776000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Education through the Basic Science Research Program","award":["NRF-2018R1D1A1A02086062"],"award-info":[{"award-number":["NRF-2018R1D1A1A02086062"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,8]]},"DOI":"10.1109\/tvlsi.2021.3086325","type":"journal-article","created":{"date-parts":[[2021,7,7]],"date-time":"2021-07-07T20:11:09Z","timestamp":1625688669000},"page":"1567-1574","source":"Crossref","is-referenced-by-count":3,"title":["A 32-Gb\/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7994-7234","authenticated-orcid":false,"given":"Junyoung","family":"Song","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sewook","family":"Hwang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4379-7905","authenticated-orcid":false,"given":"Chulwoo","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2318733"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2955389"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2882606"},{"key":"ref13","first-page":"60","article-title":"A 16-to-40 Gb\/s quarter-rate NRZ\/PAM4 dual-mode transmitter in 14 nm CMOS","author":"kim","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2216414"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2364271"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2402218"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2717900"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2695612"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265895"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757374"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662462"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2002682"},{"key":"ref5","first-page":"446","article-title":"26.5 an 8-to-16 Gb\/s 0.65-to-1.05 pJ\/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS","author":"song","year":"2014","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"588","DOI":"10.1109\/TVLSI.2014.2314147","article-title":"An 11.5 Gb\/s 1\/4th baud-rate CTLE and two-tap DFE with boosted high frequency gain in 110-nm CMOS","volume":"23","author":"kim","year":"2015","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2773642"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2520584"},{"key":"ref1","year":"2018","journal-title":"Cisco global cloud index Forecast and methodology 2016&#x2013;2021"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2771429"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2017.8240266"},{"key":"ref22","first-page":"368","article-title":"A 78 mW 11.1Gb\/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65 nm CMOS","author":"bulzacchelli","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757506"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9502420\/09477212.pdf?arnumber=9477212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:33Z","timestamp":1652194233000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9477212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,8]]},"references-count":22,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3086325","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,8]]}}}