{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T17:11:14Z","timestamp":1773249074746,"version":"3.50.1"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T00:00:00Z","timestamp":1630454400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003848","name":"Industrial Technology Research Institute","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003848","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology of Taiwan","doi-asserted-by":"publisher","award":["108-2221-E-006-147-MY2"],"award-info":[{"award-number":["108-2221-E-006-147-MY2"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,9]]},"DOI":"10.1109\/tvlsi.2021.3100343","type":"journal-article","created":{"date-parts":[[2021,8,5]],"date-time":"2021-08-05T20:17:31Z","timestamp":1628194651000},"page":"1652-1664","source":"Crossref","is-referenced-by-count":17,"title":["Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8637-2144","authenticated-orcid":false,"given":"Jai-Ming","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Yi","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao-Yuan","family":"Hsieh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ya-Ting","family":"Shyu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yeong-Jar","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juin-Ming","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.06.013"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2293422"},{"key":"ref33","first-page":"6","article-title":"3D floorplanning with thermal vias","author":"wong","year":"2006","journal-title":"Proc DATE"},{"key":"ref32","first-page":"101","article-title":"A new algorithm for floorplan design","author":"wong","year":"1986","journal-title":"Proc DAC"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883919"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/43.828554"},{"key":"ref37","first-page":"590","article-title":"3D-STAF: Scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits","author":"zhou","year":"2007","journal-title":"Proc ICCAD"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560093"},{"key":"ref35","first-page":"561","article-title":"Fixed-outline thermal-aware 3D floorplanning","author":"xiao","year":"2010","journal-title":"Proc ASP-DAC"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280818"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996800"},{"key":"ref40","year":"2021","journal-title":"IFTE-EDA\/Corblivar"},{"key":"ref11","author":"karypis","year":"2021","journal-title":"HMeTiS A Hypergraph Partitioning Package Version 1 5 3"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.846366"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432141"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388565"},{"key":"ref15","first-page":"115","article-title":"Stable-LSE based analytical placement with overlap removable length","author":"kuwano","year":"2010","journal-title":"Proc SASIMI"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379062"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2967071"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2695900"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3062669"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796761"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923063"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329460"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055179"},{"key":"ref6","first-page":"175","article-title":"A linear-time heuristic for improving network partitions","author":"fiduccia","year":"1982","journal-title":"Proc DAC"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980095"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref8","first-page":"8","article-title":"Corner block list: An effective and efficient topological representation of nonslicing floorplan","author":"hong","year":"2000","journal-title":"Proc ICCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835959"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2006043"},{"key":"ref1","first-page":"158","article-title":"Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length","author":"batude","year":"2011","journal-title":"Symp VLSI Technology Dig Technical Papers"},{"key":"ref20","article-title":"HotSpot 6.0: Validation, acceleration and extension","author":"zhang","year":"2015"},{"key":"ref22","first-page":"474","article-title":"A polynomial time primal network simplex algorithm for minimum cost flows","author":"james orlin","year":"1996","journal-title":"Proc SODA"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2942839"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2015.22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/95.679039"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796518"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2020.2970382"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9524560\/09508117.pdf?arnumber=9508117","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:34Z","timestamp":1652194234000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9508117\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9]]},"references-count":40,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3100343","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,9]]}}}