{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T14:26:09Z","timestamp":1785248769376,"version":"3.55.0"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/tvlsi.2021.3102675","type":"journal-article","created":{"date-parts":[[2021,8,13]],"date-time":"2021-08-13T20:11:31Z","timestamp":1628885491000},"page":"1707-1719","source":"Crossref","is-referenced-by-count":21,"title":["A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0698-9732","authenticated-orcid":false,"given":"M. Sultan M.","family":"Siddiqui","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhao Chuan","family":"Lee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1779-1799","authenticated-orcid":false,"given":"Tony Tae-Hyoung","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2956232"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2919104"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746310"},{"key":"ref32","first-page":"382","article-title":"A single-power-supply 0.7 V 1GHz 45 nm SRAM with an asymmetrical unit-ß-ratio memory cell","author":"kawasumi","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859025"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1987.1052809"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3044042"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705288"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2265265"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063113"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.848032"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2963704"},{"key":"ref11","first-page":"103","article-title":"A large $\\rho\\text{V}_{TH}$\n\/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme","author":"wu","year":"2010","journal-title":"IEEE VLSI Circuits Symp"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914328"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702335"},{"key":"ref14","first-page":"308","article-title":"17.2 5.6Mb\/mm2 1R1W 8T SRAM arrays operating down to 560 mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14 nm FinFET CMOS technology","author":"keane","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2018.8579292"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-018-1107-7"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.aeue.2018.12.015"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2895236"},{"key":"ref19","first-page":"232","article-title":"13.2 A 14 nm FinFET 128 Mb 6T SRAM with VMIN-enhancement techniques for low-power applications","author":"song","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","first-page":"314","article-title":"17.3 A 28 nm 256kb 6T-SRAM with 280 mV improvement in VMIN using a dual-split-control assist scheme","author":"chang","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2792428"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231322"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998187"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.917509"},{"key":"ref29","first-page":"3030","article-title":"A 0.4 V 7T SRAM with write through virtual ground and ultra-fine grain power gating switches","author":"lin yeoh","year":"2013","journal-title":"Proc IEEE Int Symp Circuits Syst (ISCAS)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310252"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.891726"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2020201"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2875934"},{"key":"ref9","first-page":"328","article-title":"A 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy","author":"verma","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.837945"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2010.5560336"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2905343"},{"key":"ref21","first-page":"176","article-title":"Two phase write scheme to improve low voltage write-ability in medium-density SRAMs","author":"sultan m siddiqui","year":"2015","journal-title":"Proc 28th Int Conf VLSI Design"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3034241"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2213513"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747151"},{"key":"ref23","first-page":"316","article-title":"A 20 nm 112 Mb SRAM in high-$\\kappa$\n metal-gate with assist circuitry for low-leakage and low-VMIN applications","author":"chang","year":"2013","journal-title":"Proc IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref26","first-page":"130c","article-title":"A 210 mV 7.3 MHz 8T SRAM with dual data-aware write-assists and negative read wordline for high cell-stability, speed and area-efficiency","author":"chen","year":"2013","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2861873"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9562994\/09513296.pdf?arnumber=9513296","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:34Z","timestamp":1652194234000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9513296\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":42,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3102675","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,10]]}}}