{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,20]],"date-time":"2026-06-20T16:22:38Z","timestamp":1781972558978,"version":"3.54.5"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"Stanford University\u2019s SystemX Alliance, the Defense Advanced Research Projects Agency","doi-asserted-by":"publisher","award":["HR0011-16-C-0044"],"award-info":[{"award-number":["HR0011-16-C-0044"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000003","name":"[Circuit Realization at Faster Timescales (CRAFT)], and the Boeing Company","doi-asserted-by":"publisher","award":["1254057"],"award-info":[{"award-number":["1254057"]}],"id":[{"id":"10.13039\/100000003","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,11]]},"DOI":"10.1109\/tvlsi.2021.3105028","type":"journal-article","created":{"date-parts":[[2021,8,27]],"date-time":"2021-08-27T20:10:51Z","timestamp":1630095051000},"page":"1838-1849","source":"Crossref","is-referenced-by-count":24,"title":["Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3683-4731","authenticated-orcid":false,"given":"Po-Hsuan","family":"Wei","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3417-8782","authenticated-orcid":false,"given":"Boris","family":"Murmann","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","first-page":"115","article-title":"Simulated binary crossover for continuous search space","volume":"9","author":"deb","year":"1995","journal-title":"Complex Syst"},{"key":"ref38","first-page":"2171","article-title":"DEAP: Evolutionary algorithms made easy","volume":"13","author":"fortin","year":"2012","journal-title":"J Mach Lang Res"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI49217.2020.00015"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1201\/9781420007954.ch5"},{"key":"ref31","year":"2021","journal-title":"How to Prioritize Specified Nets During Routing Cadence Support Resources"},{"key":"ref30","year":"2021","journal-title":"How to Keep a Group of Cells Close to One Another During Placement Cadence Support Resources"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/4235.996017"},{"key":"ref36","first-page":"55","article-title":"GANA: Graph convolutional network based automated netlist annotation for analog circuits","author":"kunal","year":"2020","journal-title":"Proc Design Automat Test Europe Conf Exhib"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1201\/9781420007954.ch8"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3032619"},{"key":"ref10","first-page":"1","article-title":"Toward silicon-proven detailed routing for analog and mixed-signal circuits","author":"chen","year":"2020","journal-title":"Proc 39th Int Conf Comput -Aided Design"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1504\/IJAISC.2014.059280"},{"key":"ref11","first-page":"1","article-title":"MAGICAL 1.0: An open-source fully-automated AMS layout synthesis framework verified with a 40-nm 1GS\/s $\\Delta\\Sigma$\n ADC","author":"chen","year":"2021","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2020.3024153"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2011.6055347"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2013.6569537"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268571"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387508"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348311"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2822811"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527229"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942062"},{"key":"ref4","article-title":"High performance PLL design in TSMC 5 nm FinFET process","author":"caplan","year":"2018","journal-title":"Proc ACM\/IEEE Design Automation Conf (DAC)"},{"key":"ref27","article-title":"Automating analog layout: Why this time is different","author":"sapatnekar","year":"0"},{"key":"ref3","author":"kawa","year":"2012","journal-title":"Designing with FinFETs The opportunities and the challenges"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2685463"},{"key":"ref29","article-title":"Row based analog standard cell layout design and methodology","author":"loh","year":"2013"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268911"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218723"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2018.8357061"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717781"},{"key":"ref9","article-title":"ALIGN: A system for automating analog layout","author":"dhar","year":"2020","journal-title":"arXiv 2008 10682"},{"key":"ref1","year":"2021","journal-title":"The McClean Report 2021"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/s10589-014-9644-1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2804220"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/CEC.2008.4631121"},{"key":"ref22","first-page":"380","article-title":"A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS","author":"bang","year":"2020","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC)"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780194"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780346"},{"key":"ref24","first-page":"141","article-title":"An open-source framework for autonomous SoC design with analog block generation","author":"ajayi","year":"2020","journal-title":"Proc IFIP Int Conf Very Large Scale Integr (VLSI-SoC)"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/4235.797969"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162800"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2647853"},{"key":"ref26","article-title":"Developing analog circuit generators using the Berkeley analog generator framework","author":"chang","year":"2019","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2939340"},{"key":"ref25","first-page":"1","article-title":"Sizing and layout integrated optimizer for 28 nm analog circuits using digital PnR tools","author":"stas","year":"2016","journal-title":"Proc 14th IEEE Int New Circuits Syst Conf (NEWCAS)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9594522\/09524486.pdf?arnumber=9524486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:21Z","timestamp":1652194221000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9524486\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11]]},"references-count":47,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3105028","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11]]}}}