{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T02:42:20Z","timestamp":1781836940460,"version":"3.54.5"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100007579","name":"Auburn University IGP grant","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007579","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/tvlsi.2021.3105958","type":"journal-article","created":{"date-parts":[[2021,9,1]],"date-time":"2021-09-01T20:22:10Z","timestamp":1630527730000},"page":"1730-1742","source":"Crossref","is-referenced-by-count":25,"title":["Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM"],"prefix":"10.1109","volume":"29","author":[{"given":"Kaniz","family":"Mishty","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0468-7810","authenticated-orcid":false,"given":"Mehdi","family":"Sadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2932285"},{"key":"ref33","first-page":"510","article-title":"True random number generation using latency variations of commercial MRAM chips","author":"ferdaus","year":"2021","journal-title":"Proc Int Symp Quality Electronic Design (ISQED)"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2900150"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2020.2995819"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS48895.2020.9073792"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1145\/3321693"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927016"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2907886"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3126908.3126964"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351201"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317874"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310393"},{"key":"ref14","first-page":"214","article-title":"A 7 Mb STT-MRAM in 22 FFL FinFET technology with 4 ns read sensing time at 0.9 V using write-verify-write scheme and offset-cancellation sensing technique","author":"wei","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062955"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993614"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993604"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.0733"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424242"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3051841"},{"key":"ref27","year":"2021","journal-title":"PyTorch"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3154484"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.053631145"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2937517"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref8","author":"wong","year":"2020","journal-title":"Stanford Memory Trends"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3012123"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref9","article-title":"Cerebras’s giant chip will smash deep learning’s speed barrier","author":"moore","year":"2020"},{"key":"ref1","article-title":"Artificial-intelligence hardware: New opportunities for semiconductor companies","author":"batra","year":"2019"},{"key":"ref20","article-title":"BFloat16: The secret to high performance on cloud TPUs","author":"wang","year":"2019"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3727\/46\/7\/074001"},{"key":"ref21","article-title":"A study of BFLOAT16 for deep learning training","author":"kalamkar","year":"2019","journal-title":"arXiv 1905 12322"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-018-32641-6"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"key":"ref26","year":"2021","journal-title":"Synopsys"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465834"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9562994\/09526872.pdf?arnumber=9526872","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:34Z","timestamp":1652194234000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9526872\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":38,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3105958","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,10]]}}}