{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T16:40:38Z","timestamp":1784220038431,"version":"3.55.0"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,10,1]],"date-time":"2021-10-01T00:00:00Z","timestamp":1633046400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Architecting More Than Moore\u2013Wireless Plasticity for Heterogeneous Massive Computer Architectures (WiPLASH) Project"},{"name":"European Union\u2019s Horizon 2020 Research and Innovation Program","award":["863337"],"award-info":[{"award-number":["863337"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,10]]},"DOI":"10.1109\/tvlsi.2021.3108806","type":"journal-article","created":{"date-parts":[[2021,9,15]],"date-time":"2021-09-15T20:11:12Z","timestamp":1631736672000},"page":"1800-1811","source":"Crossref","is-referenced-by-count":8,"title":["A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1582-0100","authenticated-orcid":false,"given":"Hayate","family":"Okuhara","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ahmed","family":"Elnaqib","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4184-2170","authenticated-orcid":false,"given":"Martino","family":"Dazzi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1672-1166","authenticated-orcid":false,"given":"Pierpaolo","family":"Palestri","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5700-5342","authenticated-orcid":false,"given":"Simone","family":"Benatti","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8068-3806","authenticated-orcid":false,"given":"Luca","family":"Benini","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0651-5393","authenticated-orcid":false,"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3005246"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2241799"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2002.1024421"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1049\/el:19750415"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181081"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1147\/rd.275.0440"},{"key":"ref36","first-page":"1","article-title":"?DMA: An autonomous I\/O subsystem for IoT end-nodes","author":"pullini","year":"2017","journal-title":"Proc 27th Int Symp Power Timing Modeling Optim Simulation (PATMOS)"},{"key":"ref35","first-page":"46","article-title":"A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14 nm tri-gate CMOS","author":"karnik","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2783680"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2009.2034764"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993643"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3045564"},{"key":"ref12","year":"2020","journal-title":"Interface Circuit for TIA\/EIA-644 (LVDS)"},{"key":"ref13","year":"2019","journal-title":"PULPissimo"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.545825"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/40.566199"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.881204"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803937"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279053"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3030243"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3349567.3351726"},{"key":"ref27","first-page":"274","article-title":"A 126 mW 56 Gb\/s NRZ wireline transceiver for synchronous short-reach applications in 16 nm FinFET","author":"erett","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","first-page":"60","article-title":"4.4 A 1.3 TOPS\/W 32 GOPS fully integrated 10-core SoC for IoT end-nodes with 1.7 ?W cognitive wake-up from MRAM-based state-retentive sleep mode","author":"rossi","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","year":"2019","journal-title":"IoT RAM & ADMUX PSRAM"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3010295"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref8","year":"2021","journal-title":"DesignWare Synchronous Serial Interface (SSI)"},{"key":"ref7","year":"2019","journal-title":"HyperRAM Memory"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2912307"},{"key":"ref9","year":"2021","journal-title":"Designware IP Datasheet USR\/XSR PHY"},{"key":"ref1","first-page":"1","article-title":"SamurAI: A 1.7 MOPS-36 GOPS adaptive versatile IoT node with 15,000&#x00D7; peak-to-idle power reduction, 207ns wake-up time and 1.3 TOPS\/W ML efficiency","author":"miro-panades","year":"2020","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref20","first-page":"1","article-title":"3.8 A 0.45-to-0.7 V 1-to-6 Gb\/S 0.29-to-0.58 pJ\/b source-synchronous transceiver using automatic phase calibration in 65 nm CMOS","author":"choi","year":"2015","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref45","year":"2021","journal-title":"3V LVDS Quad CMOS Differential Line Driver ADN4665"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351893"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2786716"},{"key":"ref42","year":"2019","journal-title":"65 nm Technology"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2936307"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2345764"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875092"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050284"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2894367"},{"key":"ref43","year":"2021","journal-title":"Analysis\/Synthesis Calculator"},{"key":"ref25","first-page":"180","article-title":"11.1 A 1.7 pJ\/b 112 Gb\/s XSR transceiver for intra-package communication in 7 nm FinFET technology","author":"yousry","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9562994\/09537900.pdf?arnumber=9537900","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:20Z","timestamp":1652194220000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9537900\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,10]]},"references-count":45,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3108806","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,10]]}}}