{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,29]],"date-time":"2025-03-29T16:46:31Z","timestamp":1743266791953,"version":"3.37.3"},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation (SRC) Center for Research in Intelligent Storage and Processing in Memory","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation (NSF) Expeditions in Computing","doi-asserted-by":"publisher","award":["CCF-1317560"],"award-info":[{"award-number":["CCF-1317560"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF Special Projects","doi-asserted-by":"publisher","award":["CCF-1955815"],"award-info":[{"award-number":["CCF-1955815"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2021,12]]},"DOI":"10.1109\/tvlsi.2021.3114186","type":"journal-article","created":{"date-parts":[[2021,10,26]],"date-time":"2021-10-26T20:47:18Z","timestamp":1635281238000},"page":"2186-2196","source":"Crossref","is-referenced-by-count":4,"title":["Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars"],"prefix":"10.1109","volume":"29","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0322-1370","authenticated-orcid":false,"given":"Nicholas","family":"Jao","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3789-7790","authenticated-orcid":false,"given":"Akshay Krishna","family":"Ramanathan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"John","family":"Sampson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6266-6068","authenticated-orcid":false,"given":"Vijaykrishnan","family":"Narayanan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2525823"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ISPDC.2012.9"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510676"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/s10994-013-5377-0"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/1553374.1553462"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3000218"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2252523"},{"key":"ref36","first-page":"1","article-title":"Full integration of highly manufacturable 512Mb PRAM based on 90 nm technology","author":"oh","year":"2006","journal-title":"IEDM Tech Dig"},{"key":"ref35","first-page":"1616","article-title":"Hardware Accelerator for Analytics of Sparse Data","author":"eriko nurvitadhi","year":"2016","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CASES.2015.7324551"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2930972"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3028506"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"journal-title":"UCI Machine Learning Repository","year":"2017","author":"dua","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268312"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.2150982"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2018.2810185"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2935890"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEMT.1997.626882"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2819080"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702534"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2754442"},{"key":"ref4","first-page":"2","article-title":"Handling PCM resistance drift with device, circuit, architecture, and system solutions","author":"awasthi","year":"2011","journal-title":"Proc Nonvolatile Memories Workshop"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2010.5510304"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168941"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00044"},{"key":"ref29","first-page":"164c","article-title":"Embedded 2 Mb ReRAM macro with 2.6 ns read access time using dynamic-trip-point-mismatch sampling current-mode sense amplifier for IoE applications","author":"lo","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2620475"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001140"},{"key":"ref7","first-page":"494","article-title":"A 65 nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16 ns multiply-and-accumulate for binary DNN AI edge processors","author":"chen","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","first-page":"28","article-title":"Learning from multiple partially observed views—an application to multilingual text categorization","author":"amini","year":"2009","journal-title":"Proc 22nd Int Conf Neural Inf Process Syst"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3005118"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3015178"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH47378.2019.181303"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00077"},{"key":"ref22","first-page":"2","article-title":"1Gbit high density embedded STT-MRAM in 28 nm FDSOI technology","author":"lee","year":"2019","journal-title":"IEDM Tech Dig"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/2600212.2600213"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2012.6398336"},{"key":"ref42","first-page":"531","article-title":"GraphR: Accelerating graph processing using ReRAM","author":"song","year":"2008","journal-title":"Proc IEEE Int Symp High Perform Comput Archit (HPCA)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00052"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00039"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.49.08JF03"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342235"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00073"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3123977"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/9627316\/9585411-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9627316\/09585411.pdf?arnumber=9585411","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T14:50:20Z","timestamp":1652194220000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9585411\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12]]},"references-count":48,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3114186","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2021,12]]}}}