{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T09:37:16Z","timestamp":1780479436754,"version":"3.54.1"},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,2,1]],"date-time":"2022-02-01T00:00:00Z","timestamp":1643673600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,2]]},"DOI":"10.1109\/tvlsi.2021.3133451","type":"journal-article","created":{"date-parts":[[2021,12,16]],"date-time":"2021-12-16T20:41:19Z","timestamp":1639687279000},"page":"123-133","source":"Crossref","is-referenced-by-count":13,"title":["A 2.56-GS\/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM<sub>\n                     <i>S<\/i>\n                  <\/sub> in 65-nm CMOS"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0939-0426","authenticated-orcid":false,"given":"Liang","family":"Fang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xianshan","family":"Wen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3822-884X","authenticated-orcid":false,"given":"Tao","family":"Fu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6130-8496","authenticated-orcid":false,"given":"Guanhua","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sandeep","family":"Miryala","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tiehui Ted","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ping","family":"Gui","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2747758"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418108"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502306"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418109"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2808244"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573537"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487818"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2912887"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642204"},{"key":"ref12","first-page":"62","article-title":"A 5 GS\/s 158.6 mW 12 b passive-sampling $8\\times$\n-interleaved hybrid ADC with 9.4 ENOB and 160.5 dB FoMS in 28 nm CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Ramkaj"},{"key":"ref13","first-page":"200","article-title":"A 1.5 mW 68 dB SNDR 80 MS\/s $2\\times$\n interleaved SAR-assisted pipelined ADC in 28 nm CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"van der Goes"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2300199"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9705196\/09653729.pdf?arnumber=9653729","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T00:30:41Z","timestamp":1704846641000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9653729\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2]]},"references-count":15,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2021.3133451","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,2]]}}}