{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:26:03Z","timestamp":1772119563931,"version":"3.50.1"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2018YFB2202602"],"award-info":[{"award-number":["2018YFB2202602"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"State Key Program of the National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61934005"],"award-info":[{"award-number":["61934005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62074001"],"award-info":[{"award-number":["62074001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Joint Funds of the National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U19A2074"],"award-info":[{"award-number":["U19A2074"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,5]]},"DOI":"10.1109\/tvlsi.2022.3148327","type":"journal-article","created":{"date-parts":[[2022,2,21]],"date-time":"2022-02-21T22:03:42Z","timestamp":1645481022000},"page":"566-578","source":"Crossref","is-referenced-by-count":11,"title":["Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3341-6294","authenticated-orcid":false,"given":"Yue","family":"Zhao","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3314-1606","authenticated-orcid":false,"given":"Zhiting","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5012-2570","authenticated-orcid":false,"given":"Xiulong","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"given":"Qiang","family":"Zhao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6201-8589","authenticated-orcid":false,"given":"Wenjuan","family":"Lu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2408-5048","authenticated-orcid":false,"given":"Chunyu","family":"Peng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8907-939X","authenticated-orcid":false,"given":"Zhongzhen","family":"Tong","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]},{"given":"Junning","family":"Chen","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Anhui University, Hefei, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939682"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2976099"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2907488"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2848999"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3005754"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2515510"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2014.6855225"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2015.7178127"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3005783"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2940649"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2928043"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310398"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2016.7573556"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2016.2545402"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2929245"},{"key":"ref22","first-page":"242","article-title":"15.3 A 351TOPS\/W and 372.4GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Dong"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3031290"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2934831"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776309"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061260"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3063719"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3056447"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISM.2010.36"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/4.982428"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2013.6519042"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2011.5750276"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.831805"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2002.1015097"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2017.8094576"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3099798"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9761844\/09718046.pdf?arnumber=9718046","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,17]],"date-time":"2024-01-17T23:30:17Z","timestamp":1705534217000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9718046\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5]]},"references-count":36,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3148327","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,5]]}}}