{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:39:14Z","timestamp":1781887154619,"version":"3.54.5"},"reference-count":56,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100018058","name":"SK Hynix Inc","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100018058","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1109\/tvlsi.2022.3153894","type":"journal-article","created":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T21:29:08Z","timestamp":1647293348000},"page":"781-793","source":"Crossref","is-referenced-by-count":13,"title":["ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6868-0829","authenticated-orcid":false,"given":"Hayoung","family":"Lee","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Younwoo","family":"Yoo","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seung Ho","family":"Shin","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7093-2095","authenticated-orcid":false,"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICISS.1997.630243"},{"key":"ref2","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"Tarr","year":"1984","journal-title":"Electronics"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294737"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.30"},{"key":"ref5","first-page":"1","article-title":"Co-architecting controllers and DRAM to enhance DRAM process scaling","volume-title":"Proc. Memory Forum","author":"Kang"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485929"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7958-2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572576"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.62132"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1983.1051979"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1137\/0108018"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1962.1057683"},{"key":"ref13","volume-title":"Memory Systems: Cache, DRAM, Disk","author":"Jacob","year":"2007"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2011.6088985"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2014.2354931"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485955"},{"key":"ref17","first-page":"318","article-title":"Pay-As-You-Go: Low-overhead hard-error correction for phase change memories","volume-title":"Proc. IEEE\/ACM Int. Symp. Microarchitecture","author":"Qureshi"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815980"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821940"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TR.1987.5222346"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2014.7087646"},{"key":"ref22","volume-title":"Low Power Double Data Rate 4(LPDDR4)","year":"2015"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2353799"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218745"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.52"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056025"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001174"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00064"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056058"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062830"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2005.18"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425789"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477302"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2015.7138734"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2925365"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2818725"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2288637"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2015.2410274"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2606499"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2017.2778301"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2920999"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2016.2624283"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1145\/2971481"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863189"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2044846"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/1897816.1897844"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1145\/2248487.2150989"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.13"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401576"},{"key":"ref52","volume-title":"PDK 45 nm Open Cell Library","year":"2011"},{"key":"ref53","volume-title":"Tessent MemoryBIST","year":"2021"},{"key":"ref54","volume-title":"Calculating Memory Power for DDR4 SDRAM","year":"2017"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2016.7483897"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.02.002"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9775758\/09733409.pdf?arnumber=9733409","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,17]],"date-time":"2024-01-17T23:45:41Z","timestamp":1705535141000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9733409\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6]]},"references-count":56,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3153894","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6]]}}}