{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:07:04Z","timestamp":1781885224605,"version":"3.54.5"},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,1]],"date-time":"2022-05-01T00:00:00Z","timestamp":1651363200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004663","name":"Young Scholar Fellowship Program by the Ministry of Science and Technology (MOST), Taiwan","doi-asserted-by":"publisher","award":["MOST110-2636-E-007-025"],"award-info":[{"award-number":["MOST110-2636-E-007-025"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004663","name":"Young Scholar Fellowship Program by the Ministry of Science and Technology (MOST), Taiwan","doi-asserted-by":"publisher","award":["MOST111-2636-E-007-023"],"award-info":[{"award-number":["MOST111-2636-E-007-023"]}],"id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,5]]},"DOI":"10.1109\/tvlsi.2022.3160327","type":"journal-article","created":{"date-parts":[[2022,3,28]],"date-time":"2022-03-28T20:59:33Z","timestamp":1648501173000},"page":"634-643","source":"Crossref","is-referenced-by-count":11,"title":["A 12\u201314.5-GHz 10.2-mW \u2212249-dB FoM Fractional-<i>N<\/i> Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7907-1685","authenticated-orcid":false,"given":"Yan-Ting","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5736-5746","authenticated-orcid":false,"given":"Pen-Jui","family":"Peng","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hung-Wen","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Yuan Ze University, Taoyuan, Taiwan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062925"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063081"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3038818"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062964"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662523"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7417910"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2478449"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2015.7313908"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2967562"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2529004"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2015.7338420"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2791486"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2823902"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2394323"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2926326"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063135"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2016.2647698"},{"key":"ref21","first-page":"366","article-title":"A 42 mW 230 fs-jitter sub-sampling 60 GHz PLL in 40 nm CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Szortyka"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2004867"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310342"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9761844\/09743562.pdf?arnumber=9743562","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T00:00:24Z","timestamp":1705536024000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9743562\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5]]},"references-count":23,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3160327","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,5]]}}}