{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T10:43:53Z","timestamp":1775817833211,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,1]],"date-time":"2022-06-01T00:00:00Z","timestamp":1654041600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1109\/tvlsi.2022.3161847","type":"journal-article","created":{"date-parts":[[2022,4,7]],"date-time":"2022-04-07T19:27:28Z","timestamp":1649359648000},"page":"755-768","source":"Crossref","is-referenced-by-count":50,"title":["Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5815-8765","authenticated-orcid":false,"given":"Souvik","family":"Kundu","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, Hyderabad, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5779-4612","authenticated-orcid":false,"given":"Priyanka B.","family":"Ganganaik","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, Hyderabad, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9487-8177","authenticated-orcid":false,"given":"Jeffry","family":"Louis","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, Hyderabad, India"}]},{"given":"Hemanth","family":"Chalamalasetty","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, Hyderabad, India"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5135-0500","authenticated-orcid":false,"given":"BVVSN Prabhakar","family":"Rao","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronics Engineering, BITS-Pilani, Hyderabad Campus, Hyderabad, India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268337"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024954"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2445572.2445577"},{"key":"ref4","volume-title":"ExaScale computing study: Technology challenges in achieving exascale systems","author":"Kogge","year":"2008"},{"key":"ref5","volume-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","year":"1996"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS46596.2019.8965179"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.032271057"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3107411.3108173"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SBAC-PAD.2016.26"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(88)90021-4"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2740343"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/34.598228"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.3390\/data4020081"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.21437\/Interspeech.2017-1363"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1001\/jamaoncol.2018.7098"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2819190"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.13"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3453688.3461494"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001139"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2776954"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2907886"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3218603.3218640"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.tjem.2018.08.001"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SIVA.2018.8661013"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.3390\/s17040712"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-48740-3_24"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1063\/1.5052619"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433536"},{"key":"ref31","first-page":"877","article-title":"Impact of process variations on emerging memristor","volume-title":"Proc. 47th Design Autom. Conf.","author":"Niu"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2000.871225"},{"key":"ref34","first-page":"96","article-title":"Low power squaring and square root circuits using subthreshold MOS transistors","volume-title":"Proc. Int. Conf. Emerg. Trends Electron. Photon. Devices Syst.","volume":"2","author":"Paily"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/BF00166411"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-015-0488-0"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1161\/01.CTR.101.23.e215"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0023610"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9775758\/09751236.pdf?arnumber=9751236","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,18]],"date-time":"2024-01-18T00:35:34Z","timestamp":1705538134000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9751236\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6]]},"references-count":38,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3161847","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,6]]}}}