{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,14]],"date-time":"2026-04-14T22:20:52Z","timestamp":1776205252151,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,7]]},"DOI":"10.1109\/tvlsi.2022.3163233","type":"journal-article","created":{"date-parts":[[2022,5,9]],"date-time":"2022-05-09T19:54:56Z","timestamp":1652126096000},"page":"869-880","source":"Crossref","is-referenced-by-count":3,"title":["MOL-Based In-Memory Computing of Binary Neural Networks"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6645-8020","authenticated-orcid":false,"given":"Khaled","family":"Alhaj Ali","sequence":"first","affiliation":[{"name":"Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6181-6500","authenticated-orcid":false,"given":"Amer","family":"Baghdadi","sequence":"additional","affiliation":[{"name":"Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2826-1416","authenticated-orcid":false,"given":"Elsa","family":"Dupraz","sequence":"additional","affiliation":[{"name":"Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9973-843X","authenticated-orcid":false,"given":"Mathieu","family":"Leonardon","sequence":"additional","affiliation":[{"name":"Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3827-7534","authenticated-orcid":false,"given":"Mostafa","family":"Rizk","sequence":"additional","affiliation":[{"name":"Lab-STICC, UMR CNRS 6285, IMT Atlantique, Brest, France"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0728-6040","authenticated-orcid":false,"given":"Jean-Philippe","family":"Diguet","sequence":"additional","affiliation":[{"name":"IRL CROSSING CNRS, Adelaide, SA, Australia"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2016.09.010"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV.2015.312"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926984"},{"key":"ref4","article-title":"Very deep convolutional networks for large-scale image recognition","author":"Simonyan","year":"2014","journal-title":"arXiv:1409.1556"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8060661"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.patcog.2020.107281"},{"key":"ref7","first-page":"3123","article-title":"Binaryconnect: Training deep neural networks with binary weights during propagations","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Courbariaux"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref9","article-title":"Binarized neural networks: Training deep neural networks with weights and activations constrained to +1 or \u22121","author":"Courbariaux","year":"2016","journal-title":"arXiv:1602.02830"},{"key":"ref10","article-title":"Towards accurate binary convolutional neural network","author":"Lin","year":"2017","journal-title":"arXiv:1711.11294"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927083"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3064189"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3011522"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2016.2570248"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2013.2282132"},{"key":"ref16","article-title":"DoReFa-net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"Zhou","year":"2016","journal-title":"arXiv:1606.06160"},{"key":"ref17","volume-title":"An intuitive explanation of convolutional neural networks","author":"Karn","year":"2016"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-46493-0_32"},{"key":"ref19","first-page":"388","article-title":"A 1 Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors","author":"Xue","year":"2019","journal-title":"IEEE ISSCC Dig. Tech. Papers"},{"key":"ref20","first-page":"28.2.1","article-title":"A 16 Mb dual-mode ReRAM macro with sub-14 ns computing-in-memory and memory functions enabled by self-write termination scheme","author":"Chen","year":"2017","journal-title":"IEDM Tech. Dig."},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2013.2296777"},{"key":"ref22","first-page":"244","article-title":"A 22 nm 2 Mb ReRAM compute-in-memory macro with 121-28TOPS\/W for multibit MAC computing for tiny AI edge devices","author":"Xue","year":"2020","journal-title":"IEEE ISSCC Dig. Tech. Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0288-0"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1049\/el.2013.2140"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898064"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1038\/nature06932"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2070050"},{"key":"ref30","volume-title":"Learning multiple layers of features from tiny images","author":"Krizhevsky","year":"2009"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116390"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3517181"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00045"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465706"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2019.2907063"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1016\/j.isci.2020.101614"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2018.8388833"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9809833\/09771078.pdf?arnumber=9771078","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T22:04:14Z","timestamp":1705961054000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9771078\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7]]},"references-count":38,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3163233","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,7]]}}}