{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T08:06:05Z","timestamp":1774944365512,"version":"3.50.1"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,8,1]],"date-time":"2022-08-01T00:00:00Z","timestamp":1659312000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation (NNSF) of China","doi-asserted-by":"publisher","award":["62176206"],"award-info":[{"award-number":["62176206"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation (NNSF) of China","doi-asserted-by":"publisher","award":["62172436"],"award-info":[{"award-number":["62172436"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004750","name":"Aeronautical Science Foundation of China","doi-asserted-by":"publisher","award":["2020Z066070001"],"award-info":[{"award-number":["2020Z066070001"]}],"id":[{"id":"10.13039\/501100004750","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Key-Area Research and Development Program of Guangdong Province","award":["2019B010154002"],"award-info":[{"award-number":["2019B010154002"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,8]]},"DOI":"10.1109\/tvlsi.2022.3166355","type":"journal-article","created":{"date-parts":[[2022,4,22]],"date-time":"2022-04-22T19:36:00Z","timestamp":1650656160000},"page":"993-1006","source":"Crossref","is-referenced-by-count":51,"title":["A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT\/INTT for Homomorphic Polynomial Multiplication"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3619-7936","authenticated-orcid":false,"given":"Yang","family":"Su","sequence":"first","affiliation":[{"name":"School of Operational Support, Rocket Force University of Engineering, Xi’an, China"}]},{"given":"Bai-Long","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Operational Support, Rocket Force University of Engineering, Xi’an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8221-7670","authenticated-orcid":false,"given":"Chen","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, China"}]},{"given":"Ze-Peng","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, China"}]},{"given":"Yi-Wei","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14623-7_25"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.4108\/eai.18-6-2016.2264201"},{"key":"ref3","first-page":"1","article-title":"CryptoNET: Design and implementation of the secure email system","volume-title":"Proc. 1st Int. Workshop Secur. Commun. Netw.","author":"Ghafoor"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1536414.1536440"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2633600"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-40041-4_5"},{"key":"ref7","first-page":"144","article-title":"Somewhat practical fully homomorphic encryption","author":"Fan","year":"2012"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70694-8_15"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-44709-3_21"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-22174-8_19"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3023255"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2018.2816640"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2019.00052"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.2988765"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378523"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2019.i4.17-61"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2983185"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116470"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig48160.2019.8994793"},{"key":"ref20","author":"Shoup","year":"2001","journal-title":"NTL: A library For Doing Number Theory"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2943127"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-33481-8_8"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474139"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-12612-4_5"},{"key":"ref25","first-page":"1","article-title":"High performance post-quantum key exchange on FPGAs","author":"Kuo","year":"2017"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i2.49-72"},{"key":"ref27","first-page":"1","article-title":"Number theoretic transform (NTT) FPGA accelerator","author":"Hartshorn","year":"2020"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2020.12.005"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3106639"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00017"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-020-01608-0"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig48160.2019.8994790"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i3.69-88"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9836323\/09761841.pdf?arnumber=9761841","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T01:10:52Z","timestamp":1706058652000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9761841\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8]]},"references-count":33,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3166355","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,8]]}}}